1*9b18e519SShengzhou Liu /* 2*9b18e519SShengzhou Liu * Cortina PHY drivers 3*9b18e519SShengzhou Liu * 4*9b18e519SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 5*9b18e519SShengzhou Liu * 6*9b18e519SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 7*9b18e519SShengzhou Liu */ 8*9b18e519SShengzhou Liu 9*9b18e519SShengzhou Liu #ifndef _CORTINA_H_ 10*9b18e519SShengzhou Liu #define _CORTINA_H_ 11*9b18e519SShengzhou Liu 12*9b18e519SShengzhou Liu #define VILLA_GLOBAL_CHIP_ID_LSB 0x000 13*9b18e519SShengzhou Liu #define VILLA_GLOBAL_CHIP_ID_MSB 0x001 14*9b18e519SShengzhou Liu #define VILLA_GLOBAL_BIST_CONTROL 0x002 15*9b18e519SShengzhou Liu #define VILLA_GLOBAL_BIST_STATUS 0x003 16*9b18e519SShengzhou Liu #define VILLA_GLOBAL_LINE_SOFT_RESET 0x007 17*9b18e519SShengzhou Liu #define VILLA_GLOBAL_HOST_SOFT_RESET 0x008 18*9b18e519SShengzhou Liu #define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A 19*9b18e519SShengzhou Liu #define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B 20*9b18e519SShengzhou Liu #define VILLA_GLOBAL_MSEQCLKCTRL 0x00E 21*9b18e519SShengzhou Liu #define VILLA_MSEQ_OPTIONS 0x1D0 22*9b18e519SShengzhou Liu #define VILLA_MSEQ_PC 0x1D3 23*9b18e519SShengzhou Liu #define VILLA_MSEQ_BANKSELECT 0x1DF 24*9b18e519SShengzhou Liu #define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB 25*9b18e519SShengzhou Liu #define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E 26*9b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403 27*9b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404 28*9b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405 29*9b18e519SShengzhou Liu #define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369 30*9b18e519SShengzhou Liu #define VILLA_MSEQ_ENABLE_MSB 0x194 31*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE21_LSB 0x226 32*9b18e519SShengzhou Liu #define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0 33*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE12_MSB 0x215 34*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE2_LSB 0x200 35*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE7_LSB 0x20A 36*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE9_LSB 0x20E 37*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE3_LSB 0x202 38*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE3_MSB 0x203 39*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE8_LSB 0x20C 40*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE8_MSB 0x20D 41*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2 42*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4 43*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6 44*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8 45*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA 46*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC 47*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0 48*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE 49*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2 50*9b18e519SShengzhou Liu #define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2 51*9b18e519SShengzhou Liu #define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360 52*9b18e519SShengzhou Liu #define VILLA_MSEQ_POWER_DOWN_LSB 0x198 53*9b18e519SShengzhou Liu #define VILLA_MSEQ_POWER_DOWN_MSB 0x199 54*9b18e519SShengzhou Liu #define VILLA_MSEQ_CAL_RX_SLICER 0x1B8 55*9b18e519SShengzhou Liu #define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365 56*9b18e519SShengzhou Liu #define VILLA_MSEQ_COEF_INIT_SEL 0x1AE 57*9b18e519SShengzhou Liu #define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A 58*9b18e519SShengzhou Liu #define VILLA_MSEQ_SERDES_PARAM_LSB 0x195 59*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE25_LSB 0x22E 60*9b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE23_LSB 0x22A 61*9b18e519SShengzhou Liu #define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA 62*9b18e519SShengzhou Liu #define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030 63*9b18e519SShengzhou Liu #define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812 64*9b18e519SShengzhou Liu #define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813 65*9b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427 66*9b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428 67*9b18e519SShengzhou Liu 68*9b18e519SShengzhou Liu #define mseq_edc_bist_done (0x1<<0) 69*9b18e519SShengzhou Liu #define mseq_edc_bist_fail (0x1<<8) 70*9b18e519SShengzhou Liu 71*9b18e519SShengzhou Liu struct cortina_reg_config { 72*9b18e519SShengzhou Liu unsigned short reg_addr; 73*9b18e519SShengzhou Liu unsigned short reg_value; 74*9b18e519SShengzhou Liu }; 75*9b18e519SShengzhou Liu #endif 76