1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 29b18e519SShengzhou Liu /* 39b18e519SShengzhou Liu * Cortina PHY drivers 49b18e519SShengzhou Liu * 59b18e519SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 69b18e519SShengzhou Liu */ 79b18e519SShengzhou Liu 89b18e519SShengzhou Liu #ifndef _CORTINA_H_ 99b18e519SShengzhou Liu #define _CORTINA_H_ 109b18e519SShengzhou Liu 119b18e519SShengzhou Liu #define VILLA_GLOBAL_CHIP_ID_LSB 0x000 129b18e519SShengzhou Liu #define VILLA_GLOBAL_CHIP_ID_MSB 0x001 139b18e519SShengzhou Liu #define VILLA_GLOBAL_BIST_CONTROL 0x002 149b18e519SShengzhou Liu #define VILLA_GLOBAL_BIST_STATUS 0x003 159b18e519SShengzhou Liu #define VILLA_GLOBAL_LINE_SOFT_RESET 0x007 169b18e519SShengzhou Liu #define VILLA_GLOBAL_HOST_SOFT_RESET 0x008 179b18e519SShengzhou Liu #define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A 189b18e519SShengzhou Liu #define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B 199b18e519SShengzhou Liu #define VILLA_GLOBAL_MSEQCLKCTRL 0x00E 209b18e519SShengzhou Liu #define VILLA_MSEQ_OPTIONS 0x1D0 219b18e519SShengzhou Liu #define VILLA_MSEQ_PC 0x1D3 229b18e519SShengzhou Liu #define VILLA_MSEQ_BANKSELECT 0x1DF 239b18e519SShengzhou Liu #define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB 249b18e519SShengzhou Liu #define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E 259b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403 269b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404 279b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405 289b18e519SShengzhou Liu #define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369 299b18e519SShengzhou Liu #define VILLA_MSEQ_ENABLE_MSB 0x194 309b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE21_LSB 0x226 319b18e519SShengzhou Liu #define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0 329b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE12_MSB 0x215 339b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE2_LSB 0x200 349b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE7_LSB 0x20A 359b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE9_LSB 0x20E 369b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE3_LSB 0x202 379b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE3_MSB 0x203 389b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE8_LSB 0x20C 399b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE8_MSB 0x20D 409b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2 419b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4 429b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6 439b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8 449b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA 459b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC 469b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0 479b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE 489b18e519SShengzhou Liu #define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2 499b18e519SShengzhou Liu #define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2 509b18e519SShengzhou Liu #define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360 519b18e519SShengzhou Liu #define VILLA_MSEQ_POWER_DOWN_LSB 0x198 529b18e519SShengzhou Liu #define VILLA_MSEQ_POWER_DOWN_MSB 0x199 539b18e519SShengzhou Liu #define VILLA_MSEQ_CAL_RX_SLICER 0x1B8 549b18e519SShengzhou Liu #define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365 559b18e519SShengzhou Liu #define VILLA_MSEQ_COEF_INIT_SEL 0x1AE 569b18e519SShengzhou Liu #define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A 579b18e519SShengzhou Liu #define VILLA_MSEQ_SERDES_PARAM_LSB 0x195 589b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE25_LSB 0x22E 599b18e519SShengzhou Liu #define VILLA_MSEQ_SPARE23_LSB 0x22A 609b18e519SShengzhou Liu #define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA 619b18e519SShengzhou Liu #define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030 629b18e519SShengzhou Liu #define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812 639b18e519SShengzhou Liu #define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813 649b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427 659b18e519SShengzhou Liu #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428 669b18e519SShengzhou Liu 679b18e519SShengzhou Liu #define mseq_edc_bist_done (0x1<<0) 689b18e519SShengzhou Liu #define mseq_edc_bist_fail (0x1<<8) 699b18e519SShengzhou Liu 709b18e519SShengzhou Liu struct cortina_reg_config { 719b18e519SShengzhou Liu unsigned short reg_addr; 729b18e519SShengzhou Liu unsigned short reg_value; 739b18e519SShengzhou Liu }; 749b18e519SShengzhou Liu #endif 75