1 /* 2 * (c) 2011 Graf-Syteco, Matthias Weisser 3 * <weisserm@arcor.de> 4 * 5 * Configuation settings for the zmx25 board 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/arch/imx-regs.h> 14 15 #define CONFIG_MX25 16 #define CONFIG_SYS_TEXT_BASE 0xA0000000 17 18 #define CONFIG_SYS_TIMER_RATE 32768 19 #define CONFIG_SYS_TIMER_COUNTER \ 20 (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) 21 22 #define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 23 /* 24 * Environment settings 25 */ 26 #define CONFIG_EXTRA_ENV_SETTINGS \ 27 "gs_fast_boot=setenv bootdelay 5\0" \ 28 "gs_slow_boot=setenv bootdelay 10\0" \ 29 "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ 30 "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ 31 "bootm 0x81000000; bootelf 0x81000000\0" 32 33 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 34 #define CONFIG_SETUP_MEMORY_TAGS 35 #define CONFIG_INITRD_TAG 36 37 /* 38 * Hardware drivers 39 */ 40 41 /* 42 * GPIO 43 */ 44 #define CONFIG_MXC_GPIO 45 46 /* 47 * Serial 48 */ 49 #define CONFIG_MXC_UART 50 #define CONFIG_MXC_UART_BASE UART2_BASE 51 #define CONFIG_CONS_INDEX 1 /* use UART2 for console */ 52 53 /* 54 * Ethernet 55 */ 56 #define CONFIG_FEC_MXC 57 #define CONFIG_FEC_MXC_PHYADDR 0x00 58 #define CONFIG_MII 59 60 /* 61 * BOOTP options 62 */ 63 #define CONFIG_BOOTP_BOOTFILESIZE 64 #define CONFIG_BOOTP_BOOTPATH 65 #define CONFIG_BOOTP_GATEWAY 66 #define CONFIG_BOOTP_HOSTNAME 67 68 /* 69 * Command line configuration. 70 */ 71 72 /* 73 * Additional command 74 */ 75 76 /* 77 * USB 78 */ 79 #ifdef CONFIG_CMD_USB 80 #define CONFIG_USB_EHCI_MXC 81 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 82 #define CONFIG_MXC_USB_PORT 1 83 #define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL 84 #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) 85 #define CONFIG_EHCI_IS_TDI 86 #define CONFIG_SUPPORT_VFAT 87 #endif /* CONFIG_CMD_USB */ 88 89 /* SDRAM */ 90 #define CONFIG_NR_DRAM_BANKS 1 91 #define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ 92 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 93 94 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 95 #define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ 96 97 /* 98 * FLASH and environment organization 99 */ 100 #define CONFIG_SYS_FLASH_BASE 0xA0000000 101 #define CONFIG_SYS_MAX_FLASH_BANKS 1 102 #define CONFIG_SYS_MAX_FLASH_SECT 256 103 104 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 105 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 106 #define CONFIG_ENV_SIZE (128 * 1024) 107 108 /* 109 * CFI FLASH driver setup 110 */ 111 #define CONFIG_SYS_FLASH_CFI 112 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */ 114 115 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 116 117 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) 118 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) 119 120 #define CONFIG_SYS_LONGHELP 121 #define CONFIG_CMDLINE_EDITING 122 123 #define CONFIG_PREBOOT "" 124 125 126 /* 127 * Size of malloc() pool 128 */ 129 #define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) 130 131 #endif /* __CONFIG_H */ 132