1 /* 2 * (c) 2011 Graf-Syteco, Matthias Weisser 3 * <weisserm@arcor.de> 4 * 5 * Configuation settings for the zmx25 board 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/arch/imx-regs.h> 14 15 #define CONFIG_MX25 16 #define CONFIG_SYS_TEXT_BASE 0xA0000000 17 18 #define CONFIG_SYS_TIMER_RATE 32768 19 #define CONFIG_SYS_TIMER_COUNTER \ 20 (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) 21 22 #define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 23 /* 24 * Environment settings 25 */ 26 #define CONFIG_EXTRA_ENV_SETTINGS \ 27 "gs_fast_boot=setenv bootdelay 5\0" \ 28 "gs_slow_boot=setenv bootdelay 10\0" \ 29 "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ 30 "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ 31 "bootm 0x81000000; bootelf 0x81000000\0" 32 33 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 34 #define CONFIG_SETUP_MEMORY_TAGS 35 #define CONFIG_INITRD_TAG 36 37 /* 38 * Compressions 39 */ 40 #define CONFIG_LZO 41 42 /* 43 * Hardware drivers 44 */ 45 46 /* 47 * GPIO 48 */ 49 #define CONFIG_MXC_GPIO 50 51 /* 52 * Serial 53 */ 54 #define CONFIG_MXC_UART 55 #define CONFIG_MXC_UART_BASE UART2_BASE 56 #define CONFIG_CONS_INDEX 1 /* use UART2 for console */ 57 58 /* 59 * Ethernet 60 */ 61 #define CONFIG_FEC_MXC 62 #define CONFIG_FEC_MXC_PHYADDR 0x00 63 #define CONFIG_MII 64 65 /* 66 * BOOTP options 67 */ 68 #define CONFIG_BOOTP_BOOTFILESIZE 69 #define CONFIG_BOOTP_BOOTPATH 70 #define CONFIG_BOOTP_GATEWAY 71 #define CONFIG_BOOTP_HOSTNAME 72 73 /* 74 * Command line configuration. 75 */ 76 77 /* 78 * Additional command 79 */ 80 81 /* 82 * USB 83 */ 84 #ifdef CONFIG_CMD_USB 85 #define CONFIG_USB_EHCI_MXC 86 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 87 #define CONFIG_MXC_USB_PORT 1 88 #define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL 89 #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) 90 #define CONFIG_EHCI_IS_TDI 91 #define CONFIG_SUPPORT_VFAT 92 #endif /* CONFIG_CMD_USB */ 93 94 /* SDRAM */ 95 #define CONFIG_NR_DRAM_BANKS 1 96 #define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ 97 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 98 99 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 100 #define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ 101 102 /* 103 * FLASH and environment organization 104 */ 105 #define CONFIG_SYS_FLASH_BASE 0xA0000000 106 #define CONFIG_SYS_MAX_FLASH_BANKS 1 107 #define CONFIG_SYS_MAX_FLASH_SECT 256 108 109 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 110 #define CONFIG_ENV_IS_IN_FLASH 1 111 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 112 #define CONFIG_ENV_SIZE (128 * 1024) 113 114 /* 115 * CFI FLASH driver setup 116 */ 117 #define CONFIG_SYS_FLASH_CFI 118 #define CONFIG_FLASH_CFI_DRIVER 119 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */ 120 121 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 122 123 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) 124 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) 125 126 #define CONFIG_SYS_CBSIZE 256 127 #define CONFIG_SYS_MAXARGS 16 128 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 129 sizeof(CONFIG_SYS_PROMPT) + 16) 130 #define CONFIG_SYS_LONGHELP 131 #define CONFIG_CMDLINE_EDITING 132 133 #define CONFIG_PREBOOT "" 134 135 136 /* 137 * Size of malloc() pool 138 */ 139 #define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) 140 141 #endif /* __CONFIG_H */ 142