1 /* 2 * (c) 2011 Graf-Syteco, Matthias Weisser 3 * <weisserm@arcor.de> 4 * 5 * Configuation settings for the zmx25 board 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <asm/arch/imx-regs.h> 14 15 #define CONFIG_SYS_TEXT_BASE 0xA0000000 16 17 #define CONFIG_SYS_TIMER_RATE 32768 18 #define CONFIG_SYS_TIMER_COUNTER \ 19 (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) 20 21 #define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 22 /* 23 * Environment settings 24 */ 25 #define CONFIG_EXTRA_ENV_SETTINGS \ 26 "gs_fast_boot=setenv bootdelay 5\0" \ 27 "gs_slow_boot=setenv bootdelay 10\0" \ 28 "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ 29 "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ 30 "bootm 0x81000000; bootelf 0x81000000\0" 31 32 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 33 #define CONFIG_SETUP_MEMORY_TAGS 34 #define CONFIG_INITRD_TAG 35 36 /* 37 * Hardware drivers 38 */ 39 40 /* 41 * Serial 42 */ 43 #define CONFIG_MXC_UART 44 #define CONFIG_MXC_UART_BASE UART2_BASE 45 #define CONFIG_CONS_INDEX 1 /* use UART2 for console */ 46 47 /* 48 * Ethernet 49 */ 50 #define CONFIG_FEC_MXC 51 #define CONFIG_FEC_MXC_PHYADDR 0x00 52 #define CONFIG_MII 53 54 /* 55 * BOOTP options 56 */ 57 #define CONFIG_BOOTP_BOOTFILESIZE 58 #define CONFIG_BOOTP_BOOTPATH 59 #define CONFIG_BOOTP_GATEWAY 60 #define CONFIG_BOOTP_HOSTNAME 61 62 /* 63 * Command line configuration. 64 */ 65 66 /* 67 * Additional command 68 */ 69 70 /* 71 * USB 72 */ 73 #ifdef CONFIG_CMD_USB 74 #define CONFIG_USB_EHCI_MXC 75 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 76 #define CONFIG_MXC_USB_PORT 1 77 #define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL 78 #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) 79 #define CONFIG_EHCI_IS_TDI 80 #endif /* CONFIG_CMD_USB */ 81 82 /* SDRAM */ 83 #define CONFIG_NR_DRAM_BANKS 1 84 #define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ 85 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 86 87 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 88 #define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ 89 90 /* 91 * FLASH and environment organization 92 */ 93 #define CONFIG_SYS_FLASH_BASE 0xA0000000 94 #define CONFIG_SYS_MAX_FLASH_BANKS 1 95 #define CONFIG_SYS_MAX_FLASH_SECT 256 96 97 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 98 #define CONFIG_ENV_SECT_SIZE (128 * 1024) 99 #define CONFIG_ENV_SIZE (128 * 1024) 100 101 /* 102 * CFI FLASH driver setup 103 */ 104 #define CONFIG_SYS_FLASH_CFI 105 #define CONFIG_FLASH_CFI_DRIVER 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */ 107 108 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 109 110 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) 111 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) 112 113 #define CONFIG_SYS_LONGHELP 114 #define CONFIG_CMDLINE_EDITING 115 116 #define CONFIG_PREBOOT "" 117 118 119 /* 120 * Size of malloc() pool 121 */ 122 #define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) 123 124 #endif /* __CONFIG_H */ 125