xref: /openbmc/u-boot/include/configs/zipitz2.h (revision 92a1babf)
1 /*
2  * Aeronix Zipit Z2 configuration file
3  *
4  * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Board Configuration Options
14  */
15 #define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
16 #define	CONFIG_SYS_TEXT_BASE		0x0
17 
18 #undef	CONFIG_SKIP_LOWLEVEL_INIT
19 #define	CONFIG_PREBOOT
20 
21 /*
22  * Environment settings
23  */
24 #define	CONFIG_ENV_OVERWRITE
25 #define CONFIG_ENV_IS_IN_FLASH		1
26 #define CONFIG_ENV_ADDR			0x40000
27 #define CONFIG_ENV_SIZE			0x10000
28 
29 #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
30 #define	CONFIG_ARCH_CPU_INIT
31 
32 #define	CONFIG_BOOTCOMMAND						\
33 	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
34 	"then "								\
35 		"source 0xa0000000; "					\
36 	"else "								\
37 		"bootm 0x50000; "					\
38 	"fi; "
39 #define	CONFIG_BOOTARGS							\
40 	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
41 #define	CONFIG_TIMESTAMP
42 #define	CONFIG_CMDLINE_TAG
43 #define	CONFIG_SETUP_MEMORY_TAGS
44 #define	CONFIG_SYS_TEXT_BASE		0x0
45 #define	CONFIG_LZMA			/* LZMA compression support */
46 
47 /*
48  * Serial Console Configuration
49  * STUART - the lower serial port on Colibri board
50  */
51 #define	CONFIG_STUART			1
52 #define CONFIG_CONS_INDEX		2
53 #define	CONFIG_BAUDRATE			115200
54 
55 /*
56  * Bootloader Components Configuration
57  */
58 #define	CONFIG_CMD_ENV
59 
60 /*
61  * MMC Card Configuration
62  */
63 #ifdef	CONFIG_CMD_MMC
64 #define	CONFIG_GENERIC_MMC
65 #define	CONFIG_PXA_MMC_GENERIC
66 #define	CONFIG_SYS_MMC_BASE		0xF0000000
67 #endif
68 
69 /*
70  * SPI and LCD
71  */
72 #ifdef	CONFIG_CMD_SPI
73 #define	CONFIG_SOFT_SPI
74 #define	CONFIG_LCD_ROTATION
75 #define	CONFIG_PXA_LCD
76 #define	CONFIG_LMS283GF05
77 
78 #define	SPI_DELAY	udelay(10)
79 #define	SPI_SDA(val)	zipitz2_spi_sda(val)
80 #define	SPI_SCL(val)	zipitz2_spi_scl(val)
81 #define	SPI_READ	zipitz2_spi_read()
82 #ifndef	__ASSEMBLY__
83 void zipitz2_spi_sda(int);
84 void zipitz2_spi_scl(int);
85 unsigned char zipitz2_spi_read(void);
86 #endif
87 #endif
88 
89 #define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
90 #define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
91 #define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
92 #define	CONFIG_SYS_MAXARGS		16		/* max number of command args */
93 #define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
94 #define	CONFIG_SYS_DEVICE_NULLDEV	1
95 
96 /*
97  * Clock Configuration
98  */
99 #define CONFIG_SYS_CPUSPEED		0x190		/* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
100 
101 /*
102  * SRAM Map
103  */
104 #define	PHYS_SRAM			0x5c000000	/* SRAM Bank #1 */
105 #define	PHYS_SRAM_SIZE			0x00040000	/* 256k */
106 
107 /*
108  * DRAM Map
109  */
110 #define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
111 #define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
112 #define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */
113 
114 #define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
115 #define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */
116 
117 #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
119 
120 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
121 
122 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
123 #define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
124 
125 /*
126  * NOR FLASH
127  */
128 #define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
129 #define PHYS_FLASH_SIZE			0x00800000	/* 8 MB */
130 #define PHYS_FLASH_SECT_SIZE		0x00010000	/* 64 KB sectors */
131 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
132 
133 #define CONFIG_SYS_FLASH_CFI
134 #define CONFIG_FLASH_CFI_DRIVER		1
135 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
136 
137 #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
138 #define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
139 
140 #define CONFIG_SYS_MAX_FLASH_BANKS	1
141 #define CONFIG_SYS_MAX_FLASH_SECT	256
142 
143 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
144 
145 #define CONFIG_SYS_FLASH_ERASE_TOUT	240000
146 #define CONFIG_SYS_FLASH_WRITE_TOUT	240000
147 #define CONFIG_SYS_FLASH_LOCK_TOUT	240000
148 #define CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
149 #define CONFIG_SYS_FLASH_PROTECTION
150 
151 /*
152  * GPIO settings
153  */
154 #define CONFIG_SYS_GAFR0_L_VAL	0x02000140
155 #define CONFIG_SYS_GAFR0_U_VAL	0x59188000
156 #define CONFIG_SYS_GAFR1_L_VAL	0x63900002
157 #define CONFIG_SYS_GAFR1_U_VAL	0xaaa03950
158 #define CONFIG_SYS_GAFR2_L_VAL	0x0aaaaaaa
159 #define CONFIG_SYS_GAFR2_U_VAL	0x29000308
160 #define CONFIG_SYS_GAFR3_L_VAL	0x54000000
161 #define CONFIG_SYS_GAFR3_U_VAL	0x000000d5
162 #define CONFIG_SYS_GPCR0_VAL	0x00000000
163 #define CONFIG_SYS_GPCR1_VAL	0x00000020
164 #define CONFIG_SYS_GPCR2_VAL	0x00000000
165 #define CONFIG_SYS_GPCR3_VAL	0x00000000
166 #define CONFIG_SYS_GPDR0_VAL	0xdafcee00
167 #define CONFIG_SYS_GPDR1_VAL	0xffa3aaab
168 #define CONFIG_SYS_GPDR2_VAL	0x8fe9ffff
169 #define CONFIG_SYS_GPDR3_VAL	0x001b1f8a
170 #define CONFIG_SYS_GPSR0_VAL	0x06080400
171 #define CONFIG_SYS_GPSR1_VAL	0x007f0000
172 #define CONFIG_SYS_GPSR2_VAL	0x032a0000
173 #define CONFIG_SYS_GPSR3_VAL	0x00000180
174 
175 #define CONFIG_SYS_PSSR_VAL	0x30
176 
177 /*
178  * Clock settings
179  */
180 #define CONFIG_SYS_CKEN		0x00511220
181 #define CONFIG_SYS_CCCR		0x00000190
182 
183 /*
184  * Memory settings
185  */
186 #define CONFIG_SYS_MSC0_VAL	0x2ffc38f8
187 #define CONFIG_SYS_MSC1_VAL	0x0000ccd1
188 #define CONFIG_SYS_MSC2_VAL	0x0000b884
189 #define CONFIG_SYS_MDCNFG_VAL	0x08000ba9
190 #define CONFIG_SYS_MDREFR_VAL	0x2011a01e
191 #define CONFIG_SYS_MDMRS_VAL	0x00000000
192 #define CONFIG_SYS_FLYCNFG_VAL	0x00010001
193 #define CONFIG_SYS_SXCNFG_VAL	0x40044004
194 
195 /*
196  * PCMCIA and CF Interfaces
197  */
198 #define CONFIG_SYS_MECR_VAL	0x00000001
199 #define CONFIG_SYS_MCMEM0_VAL	0x00014307
200 #define CONFIG_SYS_MCMEM1_VAL	0x00014307
201 #define CONFIG_SYS_MCATT0_VAL	0x0001c787
202 #define CONFIG_SYS_MCATT1_VAL	0x0001c787
203 #define CONFIG_SYS_MCIO0_VAL	0x0001430f
204 #define CONFIG_SYS_MCIO1_VAL	0x0001430f
205 
206 #include "pxa-common.h"
207 
208 #endif	/* __CONFIG_H */
209