1 /* 2 * Aeronix Zipit Z2 configuration file 3 * 4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __CONFIG_H 23 #define __CONFIG_H 24 25 /* 26 * High Level Board Configuration Options 27 */ 28 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 29 #define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */ 30 #define CONFIG_SYS_TEXT_BASE 0x0 31 32 #undef CONFIG_BOARD_LATE_INIT 33 #undef CONFIG_SKIP_LOWLEVEL_INIT 34 #define CONFIG_PREBOOT 35 36 /* 37 * Environment settings 38 */ 39 #define CONFIG_ENV_OVERWRITE 40 #define CONFIG_ENV_IS_IN_FLASH 1 41 #define CONFIG_ENV_ADDR 0x40000 42 #define CONFIG_ENV_SIZE 0x20000 43 44 /* we will never enable dcache, because we have to setup MMU first */ 45 #define CONFIG_SYS_DCACHE_OFF 46 47 #define CONFIG_SYS_MALLOC_LEN (128*1024) 48 #define CONFIG_ARCH_CPU_INIT 49 50 #define CONFIG_BOOTCOMMAND \ 51 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ 52 "then " \ 53 "source 0xa0000000; " \ 54 "else " \ 55 "bootm 0x60000; " \ 56 "fi; " 57 #define CONFIG_BOOTARGS \ 58 "console=tty0 console=ttyS2,115200 fbcon=rotate:3" 59 #define CONFIG_TIMESTAMP 60 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 61 #define CONFIG_CMDLINE_TAG 62 #define CONFIG_SETUP_MEMORY_TAGS 63 #define CONFIG_SYS_TEXT_BASE 0x0 64 #define CONFIG_LZMA /* LZMA compression support */ 65 66 /* 67 * Serial Console Configuration 68 * STUART - the lower serial port on Colibri board 69 */ 70 #define CONFIG_PXA_SERIAL 71 #define CONFIG_STUART 1 72 #define CONFIG_CONS_INDEX 2 73 #define CONFIG_BAUDRATE 115200 74 75 /* 76 * Bootloader Components Configuration 77 */ 78 #include <config_cmd_default.h> 79 80 #undef CONFIG_CMD_NET 81 #undef CONFIG_CMD_NFS 82 #define CONFIG_CMD_ENV 83 #undef CONFIG_CMD_IMLS 84 #define CONFIG_CMD_MMC 85 #define CONFIG_CMD_SPI 86 87 /* 88 * MMC Card Configuration 89 */ 90 #ifdef CONFIG_CMD_MMC 91 #define CONFIG_MMC 92 #define CONFIG_GENERIC_MMC 93 #define CONFIG_PXA_MMC_GENERIC 94 #define CONFIG_SYS_MMC_BASE 0xF0000000 95 #define CONFIG_CMD_FAT 96 #define CONFIG_CMD_EXT2 97 #define CONFIG_DOS_PARTITION 98 #endif 99 100 /* 101 * SPI and LCD 102 */ 103 #ifdef CONFIG_CMD_SPI 104 #define CONFIG_SOFT_SPI 105 #define CONFIG_LCD 106 #define CONFIG_PXA_LCD 107 #define CONFIG_LMS283GF05 108 #define CONFIG_VIDEO_LOGO 109 #define CONFIG_CMD_BMP 110 #define CONFIG_SPLASH_SCREEN 111 #define CONFIG_SPLASH_SCREEN_ALIGN 112 #define CONFIG_VIDEO_BMP_GZIP 113 #define CONFIG_VIDEO_BMP_RLE8 114 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) 115 #undef SPI_INIT 116 117 #define SPI_DELAY udelay(10) 118 #define SPI_SDA(val) zipitz2_spi_sda(val) 119 #define SPI_SCL(val) zipitz2_spi_scl(val) 120 #define SPI_READ zipitz2_spi_read() 121 #ifndef __ASSEMBLY__ 122 void zipitz2_spi_sda(int); 123 void zipitz2_spi_scl(int); 124 unsigned char zipitz2_spi_read(void); 125 #endif 126 #endif 127 128 /* 129 * KGDB 130 */ 131 #ifdef CONFIG_CMD_KGDB 132 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 133 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 134 #endif 135 136 /* 137 * HUSH Shell Configuration 138 */ 139 #define CONFIG_SYS_HUSH_PARSER 1 140 141 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 142 #ifdef CONFIG_SYS_HUSH_PARSER 143 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ 144 #else 145 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 146 #endif 147 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 148 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 149 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 150 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 151 #define CONFIG_SYS_DEVICE_NULLDEV 1 152 153 /* 154 * Clock Configuration 155 */ 156 #undef CONFIG_SYS_CLKS_IN_HZ 157 #define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ 158 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ 159 160 /* 161 * SRAM Map 162 */ 163 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ 164 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */ 165 166 /* 167 * DRAM Map 168 */ 169 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 170 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 171 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 172 173 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 174 #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ 175 176 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 177 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 178 179 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE 180 181 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 182 #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) 183 184 /* 185 * NOR FLASH 186 */ 187 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 188 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ 189 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ 190 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 191 192 #define CONFIG_SYS_FLASH_CFI 193 #define CONFIG_FLASH_CFI_DRIVER 1 194 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 195 196 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 197 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 198 199 #define CONFIG_SYS_MAX_FLASH_BANKS 1 200 #define CONFIG_SYS_MAX_FLASH_SECT 256 201 202 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 203 204 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) 205 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) 206 #define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) 207 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) 208 #define CONFIG_SYS_FLASH_PROTECTION 209 210 /* 211 * GPIO settings 212 */ 213 #define CONFIG_SYS_GAFR0_L_VAL 0x02000140 214 #define CONFIG_SYS_GAFR0_U_VAL 0x59188000 215 #define CONFIG_SYS_GAFR1_L_VAL 0x63900002 216 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 217 #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa 218 #define CONFIG_SYS_GAFR2_U_VAL 0x29000308 219 #define CONFIG_SYS_GAFR3_L_VAL 0x54000000 220 #define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 221 #define CONFIG_SYS_GPCR0_VAL 0x00000000 222 #define CONFIG_SYS_GPCR1_VAL 0x00000020 223 #define CONFIG_SYS_GPCR2_VAL 0x00000000 224 #define CONFIG_SYS_GPCR3_VAL 0x00000000 225 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 226 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab 227 #define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff 228 #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a 229 #define CONFIG_SYS_GPSR0_VAL 0x06080400 230 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 231 #define CONFIG_SYS_GPSR2_VAL 0x032a0000 232 #define CONFIG_SYS_GPSR3_VAL 0x00000180 233 234 #define CONFIG_SYS_PSSR_VAL 0x30 235 236 /* 237 * Clock settings 238 */ 239 #define CONFIG_SYS_CKEN 0x00511220 240 #define CONFIG_SYS_CCCR 0x00000190 241 242 /* 243 * Memory settings 244 */ 245 #define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 246 #define CONFIG_SYS_MSC1_VAL 0x0000ccd1 247 #define CONFIG_SYS_MSC2_VAL 0x0000b884 248 #define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 249 #define CONFIG_SYS_MDREFR_VAL 0x2011a01e 250 #define CONFIG_SYS_MDMRS_VAL 0x00000000 251 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 252 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 253 254 /* 255 * PCMCIA and CF Interfaces 256 */ 257 #define CONFIG_SYS_MECR_VAL 0x00000001 258 #define CONFIG_SYS_MCMEM0_VAL 0x00014307 259 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 260 #define CONFIG_SYS_MCATT0_VAL 0x0001c787 261 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 262 #define CONFIG_SYS_MCIO0_VAL 0x0001430f 263 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 264 265 #endif /* __CONFIG_H */ 266