1 /* 2 * Aeronix Zipit Z2 configuration file 3 * 4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Board Configuration Options 14 */ 15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 16 17 #undef CONFIG_SKIP_LOWLEVEL_INIT 18 #define CONFIG_PREBOOT 19 20 /* 21 * Environment settings 22 */ 23 #define CONFIG_ENV_OVERWRITE 24 #define CONFIG_ENV_ADDR 0x40000 25 #define CONFIG_ENV_SIZE 0x10000 26 27 #define CONFIG_SYS_MALLOC_LEN (128*1024) 28 #define CONFIG_ARCH_CPU_INIT 29 30 #define CONFIG_BOOTCOMMAND \ 31 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ 32 "then " \ 33 "source 0xa0000000; " \ 34 "else " \ 35 "bootm 0x50000; " \ 36 "fi; " 37 #define CONFIG_TIMESTAMP 38 #define CONFIG_CMDLINE_TAG 39 #define CONFIG_SETUP_MEMORY_TAGS 40 41 /* 42 * Serial Console Configuration 43 * STUART - the lower serial port on Colibri board 44 */ 45 #define CONFIG_STUART 1 46 #define CONFIG_CONS_INDEX 2 47 48 /* 49 * Bootloader Components Configuration 50 */ 51 52 /* 53 * MMC Card Configuration 54 */ 55 #ifdef CONFIG_CMD_MMC 56 #define CONFIG_PXA_MMC_GENERIC 57 #define CONFIG_SYS_MMC_BASE 0xF0000000 58 #endif 59 60 /* 61 * SPI and LCD 62 */ 63 #ifdef CONFIG_CMD_SPI 64 #define CONFIG_SOFT_SPI 65 #define CONFIG_LCD_ROTATION 66 #define CONFIG_PXA_LCD 67 #define CONFIG_LMS283GF05 68 69 #define SPI_DELAY udelay(10) 70 #define SPI_SDA(val) zipitz2_spi_sda(val) 71 #define SPI_SCL(val) zipitz2_spi_scl(val) 72 #define SPI_READ zipitz2_spi_read() 73 #ifndef __ASSEMBLY__ 74 void zipitz2_spi_sda(int); 75 void zipitz2_spi_scl(int); 76 unsigned char zipitz2_spi_read(void); 77 #endif 78 #endif 79 80 #define CONFIG_SYS_DEVICE_NULLDEV 1 81 82 /* 83 * Clock Configuration 84 */ 85 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ 86 87 /* 88 * SRAM Map 89 */ 90 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ 91 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */ 92 93 /* 94 * DRAM Map 95 */ 96 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 97 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 98 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 99 100 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 101 #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ 102 103 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 104 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 105 106 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE 107 108 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 109 #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) 110 111 /* 112 * NOR FLASH 113 */ 114 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 115 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ 116 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ 117 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 118 119 #define CONFIG_SYS_FLASH_CFI 120 #define CONFIG_FLASH_CFI_DRIVER 1 121 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 122 123 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 124 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 125 126 #define CONFIG_SYS_MAX_FLASH_BANKS 1 127 #define CONFIG_SYS_MAX_FLASH_SECT 256 128 129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 130 131 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 132 #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 133 #define CONFIG_SYS_FLASH_LOCK_TOUT 240000 134 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 135 #define CONFIG_SYS_FLASH_PROTECTION 136 137 /* 138 * GPIO settings 139 */ 140 #define CONFIG_SYS_GAFR0_L_VAL 0x02000140 141 #define CONFIG_SYS_GAFR0_U_VAL 0x59188000 142 #define CONFIG_SYS_GAFR1_L_VAL 0x63900002 143 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 144 #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa 145 #define CONFIG_SYS_GAFR2_U_VAL 0x29000308 146 #define CONFIG_SYS_GAFR3_L_VAL 0x54000000 147 #define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 148 #define CONFIG_SYS_GPCR0_VAL 0x00000000 149 #define CONFIG_SYS_GPCR1_VAL 0x00000020 150 #define CONFIG_SYS_GPCR2_VAL 0x00000000 151 #define CONFIG_SYS_GPCR3_VAL 0x00000000 152 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 153 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab 154 #define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff 155 #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a 156 #define CONFIG_SYS_GPSR0_VAL 0x06080400 157 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 158 #define CONFIG_SYS_GPSR2_VAL 0x032a0000 159 #define CONFIG_SYS_GPSR3_VAL 0x00000180 160 161 #define CONFIG_SYS_PSSR_VAL 0x30 162 163 /* 164 * Clock settings 165 */ 166 #define CONFIG_SYS_CKEN 0x00511220 167 #define CONFIG_SYS_CCCR 0x00000190 168 169 /* 170 * Memory settings 171 */ 172 #define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 173 #define CONFIG_SYS_MSC1_VAL 0x0000ccd1 174 #define CONFIG_SYS_MSC2_VAL 0x0000b884 175 #define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 176 #define CONFIG_SYS_MDREFR_VAL 0x2011a01e 177 #define CONFIG_SYS_MDMRS_VAL 0x00000000 178 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 179 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 180 181 /* 182 * PCMCIA and CF Interfaces 183 */ 184 #define CONFIG_SYS_MECR_VAL 0x00000001 185 #define CONFIG_SYS_MCMEM0_VAL 0x00014307 186 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 187 #define CONFIG_SYS_MCATT0_VAL 0x0001c787 188 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 189 #define CONFIG_SYS_MCIO0_VAL 0x0001430f 190 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 191 192 #include "pxa-common.h" 193 194 #endif /* __CONFIG_H */ 195