1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Aeronix Zipit Z2 configuration file 4 * 5 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Board Configuration Options 13 */ 14 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 15 16 #undef CONFIG_SKIP_LOWLEVEL_INIT 17 #define CONFIG_PREBOOT 18 19 /* 20 * Environment settings 21 */ 22 #define CONFIG_ENV_OVERWRITE 23 #define CONFIG_ENV_ADDR 0x40000 24 #define CONFIG_ENV_SIZE 0x10000 25 26 #define CONFIG_SYS_MALLOC_LEN (128*1024) 27 #define CONFIG_ARCH_CPU_INIT 28 29 #define CONFIG_BOOTCOMMAND \ 30 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ 31 "then " \ 32 "source 0xa0000000; " \ 33 "else " \ 34 "bootm 0x50000; " \ 35 "fi; " 36 #define CONFIG_TIMESTAMP 37 #define CONFIG_CMDLINE_TAG 38 #define CONFIG_SETUP_MEMORY_TAGS 39 40 /* 41 * Serial Console Configuration 42 * STUART - the lower serial port on Colibri board 43 */ 44 #define CONFIG_STUART 1 45 46 /* 47 * Bootloader Components Configuration 48 */ 49 50 /* 51 * MMC Card Configuration 52 */ 53 #ifdef CONFIG_CMD_MMC 54 #define CONFIG_PXA_MMC_GENERIC 55 #define CONFIG_SYS_MMC_BASE 0xF0000000 56 #endif 57 58 /* 59 * SPI and LCD 60 */ 61 #ifdef CONFIG_CMD_SPI 62 #define CONFIG_SOFT_SPI 63 #define CONFIG_LCD_ROTATION 64 #define CONFIG_PXA_LCD 65 #define CONFIG_LMS283GF05 66 67 #define SPI_DELAY udelay(10) 68 #define SPI_SDA(val) zipitz2_spi_sda(val) 69 #define SPI_SCL(val) zipitz2_spi_scl(val) 70 #define SPI_READ zipitz2_spi_read() 71 #ifndef __ASSEMBLY__ 72 void zipitz2_spi_sda(int); 73 void zipitz2_spi_scl(int); 74 unsigned char zipitz2_spi_read(void); 75 #endif 76 #endif 77 78 #define CONFIG_SYS_DEVICE_NULLDEV 1 79 80 /* 81 * Clock Configuration 82 */ 83 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ 84 85 /* 86 * SRAM Map 87 */ 88 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ 89 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */ 90 91 /* 92 * DRAM Map 93 */ 94 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 95 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 96 97 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 98 #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ 99 100 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 101 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 102 103 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE 104 105 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 106 #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) 107 108 /* 109 * NOR FLASH 110 */ 111 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 112 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ 113 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ 114 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 115 116 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 117 118 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 119 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 120 121 #define CONFIG_SYS_MAX_FLASH_BANKS 1 122 #define CONFIG_SYS_MAX_FLASH_SECT 256 123 124 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 125 #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 126 #define CONFIG_SYS_FLASH_LOCK_TOUT 240000 127 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 128 129 /* 130 * GPIO settings 131 */ 132 #define CONFIG_SYS_GAFR0_L_VAL 0x02000140 133 #define CONFIG_SYS_GAFR0_U_VAL 0x59188000 134 #define CONFIG_SYS_GAFR1_L_VAL 0x63900002 135 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 136 #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa 137 #define CONFIG_SYS_GAFR2_U_VAL 0x29000308 138 #define CONFIG_SYS_GAFR3_L_VAL 0x54000000 139 #define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 140 #define CONFIG_SYS_GPCR0_VAL 0x00000000 141 #define CONFIG_SYS_GPCR1_VAL 0x00000020 142 #define CONFIG_SYS_GPCR2_VAL 0x00000000 143 #define CONFIG_SYS_GPCR3_VAL 0x00000000 144 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 145 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab 146 #define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff 147 #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a 148 #define CONFIG_SYS_GPSR0_VAL 0x06080400 149 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 150 #define CONFIG_SYS_GPSR2_VAL 0x032a0000 151 #define CONFIG_SYS_GPSR3_VAL 0x00000180 152 153 #define CONFIG_SYS_PSSR_VAL 0x30 154 155 /* 156 * Clock settings 157 */ 158 #define CONFIG_SYS_CKEN 0x00511220 159 #define CONFIG_SYS_CCCR 0x00000190 160 161 /* 162 * Memory settings 163 */ 164 #define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 165 #define CONFIG_SYS_MSC1_VAL 0x0000ccd1 166 #define CONFIG_SYS_MSC2_VAL 0x0000b884 167 #define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 168 #define CONFIG_SYS_MDREFR_VAL 0x2011a01e 169 #define CONFIG_SYS_MDMRS_VAL 0x00000000 170 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 171 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 172 173 /* 174 * PCMCIA and CF Interfaces 175 */ 176 #define CONFIG_SYS_MECR_VAL 0x00000001 177 #define CONFIG_SYS_MCMEM0_VAL 0x00014307 178 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 179 #define CONFIG_SYS_MCATT0_VAL 0x0001c787 180 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 181 #define CONFIG_SYS_MCIO0_VAL 0x0001430f 182 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 183 184 #include "pxa-common.h" 185 186 #endif /* __CONFIG_H */ 187