1 /* 2 * Aeronix Zipit Z2 configuration file 3 * 4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Board Configuration Options 14 */ 15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 16 #define CONFIG_SYS_TEXT_BASE 0x0 17 18 #undef CONFIG_SKIP_LOWLEVEL_INIT 19 #define CONFIG_PREBOOT 20 21 /* 22 * Environment settings 23 */ 24 #define CONFIG_ENV_OVERWRITE 25 #define CONFIG_ENV_IS_IN_FLASH 1 26 #define CONFIG_ENV_ADDR 0x40000 27 #define CONFIG_ENV_SIZE 0x10000 28 29 #define CONFIG_SYS_MALLOC_LEN (128*1024) 30 #define CONFIG_ARCH_CPU_INIT 31 32 #define CONFIG_BOOTCOMMAND \ 33 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ 34 "then " \ 35 "source 0xa0000000; " \ 36 "else " \ 37 "bootm 0x50000; " \ 38 "fi; " 39 #define CONFIG_BOOTARGS \ 40 "console=tty0 console=ttyS2,115200 fbcon=rotate:3" 41 #define CONFIG_TIMESTAMP 42 #define CONFIG_CMDLINE_TAG 43 #define CONFIG_SETUP_MEMORY_TAGS 44 #define CONFIG_SYS_TEXT_BASE 0x0 45 46 /* 47 * Serial Console Configuration 48 * STUART - the lower serial port on Colibri board 49 */ 50 #define CONFIG_STUART 1 51 #define CONFIG_CONS_INDEX 2 52 53 /* 54 * Bootloader Components Configuration 55 */ 56 57 /* 58 * MMC Card Configuration 59 */ 60 #ifdef CONFIG_CMD_MMC 61 #define CONFIG_PXA_MMC_GENERIC 62 #define CONFIG_SYS_MMC_BASE 0xF0000000 63 #endif 64 65 /* 66 * SPI and LCD 67 */ 68 #ifdef CONFIG_CMD_SPI 69 #define CONFIG_SOFT_SPI 70 #define CONFIG_LCD_ROTATION 71 #define CONFIG_PXA_LCD 72 #define CONFIG_LMS283GF05 73 74 #define SPI_DELAY udelay(10) 75 #define SPI_SDA(val) zipitz2_spi_sda(val) 76 #define SPI_SCL(val) zipitz2_spi_scl(val) 77 #define SPI_READ zipitz2_spi_read() 78 #ifndef __ASSEMBLY__ 79 void zipitz2_spi_sda(int); 80 void zipitz2_spi_scl(int); 81 unsigned char zipitz2_spi_read(void); 82 #endif 83 #endif 84 85 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 86 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 87 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 88 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 89 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 90 #define CONFIG_SYS_DEVICE_NULLDEV 1 91 92 /* 93 * Clock Configuration 94 */ 95 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ 96 97 /* 98 * SRAM Map 99 */ 100 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ 101 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */ 102 103 /* 104 * DRAM Map 105 */ 106 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 107 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 108 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 109 110 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 111 #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ 112 113 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 114 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 115 116 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE 117 118 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 119 #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) 120 121 /* 122 * NOR FLASH 123 */ 124 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 125 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ 126 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ 127 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 128 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_FLASH_CFI_DRIVER 1 131 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 132 133 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 134 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 135 136 #define CONFIG_SYS_MAX_FLASH_BANKS 1 137 #define CONFIG_SYS_MAX_FLASH_SECT 256 138 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 140 141 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 142 #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 143 #define CONFIG_SYS_FLASH_LOCK_TOUT 240000 144 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 145 #define CONFIG_SYS_FLASH_PROTECTION 146 147 /* 148 * GPIO settings 149 */ 150 #define CONFIG_SYS_GAFR0_L_VAL 0x02000140 151 #define CONFIG_SYS_GAFR0_U_VAL 0x59188000 152 #define CONFIG_SYS_GAFR1_L_VAL 0x63900002 153 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 154 #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa 155 #define CONFIG_SYS_GAFR2_U_VAL 0x29000308 156 #define CONFIG_SYS_GAFR3_L_VAL 0x54000000 157 #define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 158 #define CONFIG_SYS_GPCR0_VAL 0x00000000 159 #define CONFIG_SYS_GPCR1_VAL 0x00000020 160 #define CONFIG_SYS_GPCR2_VAL 0x00000000 161 #define CONFIG_SYS_GPCR3_VAL 0x00000000 162 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 163 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab 164 #define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff 165 #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a 166 #define CONFIG_SYS_GPSR0_VAL 0x06080400 167 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 168 #define CONFIG_SYS_GPSR2_VAL 0x032a0000 169 #define CONFIG_SYS_GPSR3_VAL 0x00000180 170 171 #define CONFIG_SYS_PSSR_VAL 0x30 172 173 /* 174 * Clock settings 175 */ 176 #define CONFIG_SYS_CKEN 0x00511220 177 #define CONFIG_SYS_CCCR 0x00000190 178 179 /* 180 * Memory settings 181 */ 182 #define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 183 #define CONFIG_SYS_MSC1_VAL 0x0000ccd1 184 #define CONFIG_SYS_MSC2_VAL 0x0000b884 185 #define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 186 #define CONFIG_SYS_MDREFR_VAL 0x2011a01e 187 #define CONFIG_SYS_MDMRS_VAL 0x00000000 188 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 189 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 190 191 /* 192 * PCMCIA and CF Interfaces 193 */ 194 #define CONFIG_SYS_MECR_VAL 0x00000001 195 #define CONFIG_SYS_MCMEM0_VAL 0x00014307 196 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 197 #define CONFIG_SYS_MCATT0_VAL 0x0001c787 198 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 199 #define CONFIG_SYS_MCIO0_VAL 0x0001430f 200 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 201 202 #include "pxa-common.h" 203 204 #endif /* __CONFIG_H */ 205