1 /* 2 * Aeronix Zipit Z2 configuration file 3 * 4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Board Configuration Options 14 */ 15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 16 #define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */ 17 #define CONFIG_SYS_TEXT_BASE 0x0 18 19 #undef CONFIG_BOARD_LATE_INIT 20 #undef CONFIG_SKIP_LOWLEVEL_INIT 21 #define CONFIG_PREBOOT 22 23 /* 24 * Environment settings 25 */ 26 #define CONFIG_ENV_OVERWRITE 27 #define CONFIG_ENV_IS_IN_FLASH 1 28 #define CONFIG_ENV_ADDR 0x40000 29 #define CONFIG_ENV_SIZE 0x20000 30 31 /* we will never enable dcache, because we have to setup MMU first */ 32 #define CONFIG_SYS_DCACHE_OFF 33 34 #define CONFIG_SYS_MALLOC_LEN (128*1024) 35 #define CONFIG_ARCH_CPU_INIT 36 37 #define CONFIG_BOOTCOMMAND \ 38 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ 39 "then " \ 40 "source 0xa0000000; " \ 41 "else " \ 42 "bootm 0x60000; " \ 43 "fi; " 44 #define CONFIG_BOOTARGS \ 45 "console=tty0 console=ttyS2,115200 fbcon=rotate:3" 46 #define CONFIG_TIMESTAMP 47 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 48 #define CONFIG_CMDLINE_TAG 49 #define CONFIG_SETUP_MEMORY_TAGS 50 #define CONFIG_SYS_TEXT_BASE 0x0 51 #define CONFIG_LZMA /* LZMA compression support */ 52 53 /* 54 * Serial Console Configuration 55 * STUART - the lower serial port on Colibri board 56 */ 57 #define CONFIG_PXA_SERIAL 58 #define CONFIG_STUART 1 59 #define CONFIG_CONS_INDEX 2 60 #define CONFIG_BAUDRATE 115200 61 62 /* 63 * Bootloader Components Configuration 64 */ 65 #include <config_cmd_default.h> 66 67 #undef CONFIG_CMD_NFS 68 #define CONFIG_CMD_ENV 69 #undef CONFIG_CMD_IMLS 70 #define CONFIG_CMD_MMC 71 #define CONFIG_CMD_SPI 72 73 /* 74 * MMC Card Configuration 75 */ 76 #ifdef CONFIG_CMD_MMC 77 #define CONFIG_MMC 78 #define CONFIG_GENERIC_MMC 79 #define CONFIG_PXA_MMC_GENERIC 80 #define CONFIG_SYS_MMC_BASE 0xF0000000 81 #define CONFIG_CMD_FAT 82 #define CONFIG_CMD_EXT2 83 #define CONFIG_DOS_PARTITION 84 #endif 85 86 /* 87 * SPI and LCD 88 */ 89 #ifdef CONFIG_CMD_SPI 90 #define CONFIG_SOFT_SPI 91 #define CONFIG_LCD 92 #define CONFIG_PXA_LCD 93 #define CONFIG_LMS283GF05 94 #define CONFIG_VIDEO_LOGO 95 #define CONFIG_CMD_BMP 96 #define CONFIG_SPLASH_SCREEN 97 #define CONFIG_SPLASH_SCREEN_ALIGN 98 #define CONFIG_VIDEO_BMP_GZIP 99 #define CONFIG_VIDEO_BMP_RLE8 100 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) 101 102 #define SPI_DELAY udelay(10) 103 #define SPI_SDA(val) zipitz2_spi_sda(val) 104 #define SPI_SCL(val) zipitz2_spi_scl(val) 105 #define SPI_READ zipitz2_spi_read() 106 #ifndef __ASSEMBLY__ 107 void zipitz2_spi_sda(int); 108 void zipitz2_spi_scl(int); 109 unsigned char zipitz2_spi_read(void); 110 #endif 111 #endif 112 113 /* 114 * KGDB 115 */ 116 #ifdef CONFIG_CMD_KGDB 117 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 118 #endif 119 120 /* 121 * HUSH Shell Configuration 122 */ 123 #define CONFIG_SYS_HUSH_PARSER 1 124 125 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 126 #ifdef CONFIG_SYS_HUSH_PARSER 127 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ 128 #endif 129 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 131 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 132 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 133 #define CONFIG_SYS_DEVICE_NULLDEV 1 134 135 /* 136 * Clock Configuration 137 */ 138 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ 139 140 /* 141 * SRAM Map 142 */ 143 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ 144 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */ 145 146 /* 147 * DRAM Map 148 */ 149 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 150 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 151 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 152 153 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 154 #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ 155 156 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 157 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 158 159 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE 160 161 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 162 #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) 163 164 /* 165 * NOR FLASH 166 */ 167 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 168 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ 169 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ 170 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 171 172 #define CONFIG_SYS_FLASH_CFI 173 #define CONFIG_FLASH_CFI_DRIVER 1 174 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 175 176 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 177 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 178 179 #define CONFIG_SYS_MAX_FLASH_BANKS 1 180 #define CONFIG_SYS_MAX_FLASH_SECT 256 181 182 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 183 184 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 185 #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 186 #define CONFIG_SYS_FLASH_LOCK_TOUT 240000 187 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 188 #define CONFIG_SYS_FLASH_PROTECTION 189 190 /* 191 * GPIO settings 192 */ 193 #define CONFIG_SYS_GAFR0_L_VAL 0x02000140 194 #define CONFIG_SYS_GAFR0_U_VAL 0x59188000 195 #define CONFIG_SYS_GAFR1_L_VAL 0x63900002 196 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 197 #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa 198 #define CONFIG_SYS_GAFR2_U_VAL 0x29000308 199 #define CONFIG_SYS_GAFR3_L_VAL 0x54000000 200 #define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 201 #define CONFIG_SYS_GPCR0_VAL 0x00000000 202 #define CONFIG_SYS_GPCR1_VAL 0x00000020 203 #define CONFIG_SYS_GPCR2_VAL 0x00000000 204 #define CONFIG_SYS_GPCR3_VAL 0x00000000 205 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 206 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab 207 #define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff 208 #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a 209 #define CONFIG_SYS_GPSR0_VAL 0x06080400 210 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 211 #define CONFIG_SYS_GPSR2_VAL 0x032a0000 212 #define CONFIG_SYS_GPSR3_VAL 0x00000180 213 214 #define CONFIG_SYS_PSSR_VAL 0x30 215 216 /* 217 * Clock settings 218 */ 219 #define CONFIG_SYS_CKEN 0x00511220 220 #define CONFIG_SYS_CCCR 0x00000190 221 222 /* 223 * Memory settings 224 */ 225 #define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 226 #define CONFIG_SYS_MSC1_VAL 0x0000ccd1 227 #define CONFIG_SYS_MSC2_VAL 0x0000b884 228 #define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 229 #define CONFIG_SYS_MDREFR_VAL 0x2011a01e 230 #define CONFIG_SYS_MDMRS_VAL 0x00000000 231 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 232 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 233 234 /* 235 * PCMCIA and CF Interfaces 236 */ 237 #define CONFIG_SYS_MECR_VAL 0x00000001 238 #define CONFIG_SYS_MCMEM0_VAL 0x00014307 239 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 240 #define CONFIG_SYS_MCATT0_VAL 0x0001c787 241 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 242 #define CONFIG_SYS_MCIO0_VAL 0x0001430f 243 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 244 245 #endif /* __CONFIG_H */ 246