1 /* 2 * Aeronix Zipit Z2 configuration file 3 * 4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Board Configuration Options 14 */ 15 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 16 #define CONFIG_SYS_TEXT_BASE 0x0 17 18 #undef CONFIG_BOARD_LATE_INIT 19 #undef CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_PREBOOT 21 22 /* 23 * Environment settings 24 */ 25 #define CONFIG_ENV_OVERWRITE 26 #define CONFIG_ENV_IS_IN_FLASH 1 27 #define CONFIG_ENV_ADDR 0x40000 28 #define CONFIG_ENV_SIZE 0x10000 29 30 #define CONFIG_SYS_MALLOC_LEN (128*1024) 31 #define CONFIG_ARCH_CPU_INIT 32 33 #define CONFIG_BOOTCOMMAND \ 34 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ 35 "then " \ 36 "source 0xa0000000; " \ 37 "else " \ 38 "bootm 0x50000; " \ 39 "fi; " 40 #define CONFIG_BOOTARGS \ 41 "console=tty0 console=ttyS2,115200 fbcon=rotate:3" 42 #define CONFIG_TIMESTAMP 43 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 44 #define CONFIG_CMDLINE_TAG 45 #define CONFIG_SETUP_MEMORY_TAGS 46 #define CONFIG_SYS_TEXT_BASE 0x0 47 #define CONFIG_LZMA /* LZMA compression support */ 48 #define CONFIG_OF_LIBFDT 49 50 /* 51 * Serial Console Configuration 52 * STUART - the lower serial port on Colibri board 53 */ 54 #define CONFIG_PXA_SERIAL 55 #define CONFIG_STUART 1 56 #define CONFIG_CONS_INDEX 2 57 #define CONFIG_BAUDRATE 115200 58 59 /* 60 * Bootloader Components Configuration 61 */ 62 #define CONFIG_CMD_ENV 63 #define CONFIG_CMD_MMC 64 #define CONFIG_CMD_SPI 65 #define CONFIG_CMD_USB 66 #define CONFIG_CMD_CACHE 67 68 /* 69 * MMC Card Configuration 70 */ 71 #ifdef CONFIG_CMD_MMC 72 #define CONFIG_MMC 73 #define CONFIG_GENERIC_MMC 74 #define CONFIG_PXA_MMC_GENERIC 75 #define CONFIG_SYS_MMC_BASE 0xF0000000 76 #define CONFIG_CMD_FAT 77 #define CONFIG_CMD_EXT2 78 #define CONFIG_DOS_PARTITION 79 #endif 80 81 /* 82 * SPI and LCD 83 */ 84 #ifdef CONFIG_CMD_SPI 85 #define CONFIG_SOFT_SPI 86 #define CONFIG_LCD 87 #define CONFIG_LCD_ROTATION 88 #define CONFIG_PXA_LCD 89 #define CONFIG_LMS283GF05 90 91 #define SPI_DELAY udelay(10) 92 #define SPI_SDA(val) zipitz2_spi_sda(val) 93 #define SPI_SCL(val) zipitz2_spi_scl(val) 94 #define SPI_READ zipitz2_spi_read() 95 #ifndef __ASSEMBLY__ 96 void zipitz2_spi_sda(int); 97 void zipitz2_spi_scl(int); 98 unsigned char zipitz2_spi_read(void); 99 #endif 100 #endif 101 102 /* 103 * HUSH Shell Configuration 104 */ 105 #define CONFIG_SYS_HUSH_PARSER 1 106 107 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 108 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 110 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 112 #define CONFIG_SYS_DEVICE_NULLDEV 1 113 114 /* 115 * Clock Configuration 116 */ 117 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ 118 119 /* 120 * SRAM Map 121 */ 122 #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ 123 #define PHYS_SRAM_SIZE 0x00040000 /* 256k */ 124 125 /* 126 * DRAM Map 127 */ 128 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 129 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 130 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 131 132 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 133 #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ 134 135 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 136 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 137 138 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE 139 140 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 141 #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) 142 143 /* 144 * NOR FLASH 145 */ 146 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 147 #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ 148 #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ 149 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 150 151 #define CONFIG_SYS_FLASH_CFI 152 #define CONFIG_FLASH_CFI_DRIVER 1 153 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 154 155 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 156 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 157 158 #define CONFIG_SYS_MAX_FLASH_BANKS 1 159 #define CONFIG_SYS_MAX_FLASH_SECT 256 160 161 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 162 163 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 164 #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 165 #define CONFIG_SYS_FLASH_LOCK_TOUT 240000 166 #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 167 #define CONFIG_SYS_FLASH_PROTECTION 168 169 /* 170 * GPIO settings 171 */ 172 #define CONFIG_SYS_GAFR0_L_VAL 0x02000140 173 #define CONFIG_SYS_GAFR0_U_VAL 0x59188000 174 #define CONFIG_SYS_GAFR1_L_VAL 0x63900002 175 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 176 #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa 177 #define CONFIG_SYS_GAFR2_U_VAL 0x29000308 178 #define CONFIG_SYS_GAFR3_L_VAL 0x54000000 179 #define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 180 #define CONFIG_SYS_GPCR0_VAL 0x00000000 181 #define CONFIG_SYS_GPCR1_VAL 0x00000020 182 #define CONFIG_SYS_GPCR2_VAL 0x00000000 183 #define CONFIG_SYS_GPCR3_VAL 0x00000000 184 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 185 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab 186 #define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff 187 #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a 188 #define CONFIG_SYS_GPSR0_VAL 0x06080400 189 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 190 #define CONFIG_SYS_GPSR2_VAL 0x032a0000 191 #define CONFIG_SYS_GPSR3_VAL 0x00000180 192 193 #define CONFIG_SYS_PSSR_VAL 0x30 194 195 /* 196 * Clock settings 197 */ 198 #define CONFIG_SYS_CKEN 0x00511220 199 #define CONFIG_SYS_CCCR 0x00000190 200 201 /* 202 * Memory settings 203 */ 204 #define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 205 #define CONFIG_SYS_MSC1_VAL 0x0000ccd1 206 #define CONFIG_SYS_MSC2_VAL 0x0000b884 207 #define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 208 #define CONFIG_SYS_MDREFR_VAL 0x2011a01e 209 #define CONFIG_SYS_MDMRS_VAL 0x00000000 210 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 211 #define CONFIG_SYS_SXCNFG_VAL 0x40044004 212 213 /* 214 * PCMCIA and CF Interfaces 215 */ 216 #define CONFIG_SYS_MECR_VAL 0x00000001 217 #define CONFIG_SYS_MCMEM0_VAL 0x00014307 218 #define CONFIG_SYS_MCMEM1_VAL 0x00014307 219 #define CONFIG_SYS_MCATT0_VAL 0x0001c787 220 #define CONFIG_SYS_MCATT1_VAL 0x0001c787 221 #define CONFIG_SYS_MCIO0_VAL 0x0001430f 222 #define CONFIG_SYS_MCIO1_VAL 0x0001430f 223 224 #include "pxa-common.h" 225 226 #endif /* __CONFIG_H */ 227