1*f19eb154SVasily Khoruzhick /* 2*f19eb154SVasily Khoruzhick * Aeronix Zipit Z2 configuration file 3*f19eb154SVasily Khoruzhick * 4*f19eb154SVasily Khoruzhick * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> 5*f19eb154SVasily Khoruzhick * 6*f19eb154SVasily Khoruzhick * SPDX-License-Identifier: GPL-2.0+ 7*f19eb154SVasily Khoruzhick */ 8*f19eb154SVasily Khoruzhick 9*f19eb154SVasily Khoruzhick #ifndef __CONFIG_H 10*f19eb154SVasily Khoruzhick #define __CONFIG_H 11*f19eb154SVasily Khoruzhick 12*f19eb154SVasily Khoruzhick /* 13*f19eb154SVasily Khoruzhick * High Level Board Configuration Options 14*f19eb154SVasily Khoruzhick */ 15*f19eb154SVasily Khoruzhick #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ 16*f19eb154SVasily Khoruzhick #define CONFIG_SYS_TEXT_BASE 0x0 17*f19eb154SVasily Khoruzhick 18*f19eb154SVasily Khoruzhick #undef CONFIG_BOARD_LATE_INIT 19*f19eb154SVasily Khoruzhick #undef CONFIG_SKIP_LOWLEVEL_INIT 20*f19eb154SVasily Khoruzhick #define CONFIG_PREBOOT 21*f19eb154SVasily Khoruzhick 22*f19eb154SVasily Khoruzhick /* 23*f19eb154SVasily Khoruzhick * Environment settings 24*f19eb154SVasily Khoruzhick */ 25*f19eb154SVasily Khoruzhick #define CONFIG_ENV_OVERWRITE 26*f19eb154SVasily Khoruzhick #define CONFIG_ENV_IS_IN_FLASH 1 27*f19eb154SVasily Khoruzhick #define CONFIG_ENV_ADDR 0x40000 28*f19eb154SVasily Khoruzhick #define CONFIG_ENV_SIZE 0x10000 29*f19eb154SVasily Khoruzhick 30*f19eb154SVasily Khoruzhick #define CONFIG_SYS_DCACHE_OFF 31*f19eb154SVasily Khoruzhick 32*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MALLOC_LEN (128*1024) 33*f19eb154SVasily Khoruzhick #define CONFIG_ARCH_CPU_INIT 34*f19eb154SVasily Khoruzhick 35*f19eb154SVasily Khoruzhick #define CONFIG_BOOTCOMMAND \ 36*f19eb154SVasily Khoruzhick "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ 37*f19eb154SVasily Khoruzhick "then " \ 38*f19eb154SVasily Khoruzhick "source 0xa0000000; " \ 39*f19eb154SVasily Khoruzhick "else " \ 40*f19eb154SVasily Khoruzhick "bootm 0x50000; " \ 41*f19eb154SVasily Khoruzhick "fi; " 42*f19eb154SVasily Khoruzhick #define CONFIG_BOOTARGS \ 43*f19eb154SVasily Khoruzhick "console=tty0 console=ttyS2,115200 fbcon=rotate:3" 44*f19eb154SVasily Khoruzhick #define CONFIG_TIMESTAMP 45*f19eb154SVasily Khoruzhick #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ 46*f19eb154SVasily Khoruzhick #define CONFIG_CMDLINE_TAG 47*f19eb154SVasily Khoruzhick #define CONFIG_SETUP_MEMORY_TAGS 48*f19eb154SVasily Khoruzhick #define CONFIG_SYS_TEXT_BASE 0x0 49*f19eb154SVasily Khoruzhick #define CONFIG_LZMA /* LZMA compression support */ 50*f19eb154SVasily Khoruzhick 51*f19eb154SVasily Khoruzhick /* 52*f19eb154SVasily Khoruzhick * Serial Console Configuration 53*f19eb154SVasily Khoruzhick * STUART - the lower serial port on Colibri board 54*f19eb154SVasily Khoruzhick */ 55*f19eb154SVasily Khoruzhick #define CONFIG_PXA_SERIAL 56*f19eb154SVasily Khoruzhick #define CONFIG_STUART 1 57*f19eb154SVasily Khoruzhick #define CONFIG_CONS_INDEX 2 58*f19eb154SVasily Khoruzhick #define CONFIG_BAUDRATE 115200 59*f19eb154SVasily Khoruzhick 60*f19eb154SVasily Khoruzhick /* 61*f19eb154SVasily Khoruzhick * Bootloader Components Configuration 62*f19eb154SVasily Khoruzhick */ 63*f19eb154SVasily Khoruzhick #define CONFIG_CMD_ENV 64*f19eb154SVasily Khoruzhick #define CONFIG_CMD_MMC 65*f19eb154SVasily Khoruzhick #define CONFIG_CMD_SPI 66*f19eb154SVasily Khoruzhick 67*f19eb154SVasily Khoruzhick /* 68*f19eb154SVasily Khoruzhick * MMC Card Configuration 69*f19eb154SVasily Khoruzhick */ 70*f19eb154SVasily Khoruzhick #ifdef CONFIG_CMD_MMC 71*f19eb154SVasily Khoruzhick #define CONFIG_MMC 72*f19eb154SVasily Khoruzhick #define CONFIG_GENERIC_MMC 73*f19eb154SVasily Khoruzhick #define CONFIG_PXA_MMC_GENERIC 74*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MMC_BASE 0xF0000000 75*f19eb154SVasily Khoruzhick #define CONFIG_CMD_FAT 76*f19eb154SVasily Khoruzhick #define CONFIG_CMD_EXT2 77*f19eb154SVasily Khoruzhick #define CONFIG_DOS_PARTITION 78*f19eb154SVasily Khoruzhick #endif 79*f19eb154SVasily Khoruzhick 80*f19eb154SVasily Khoruzhick /* 81*f19eb154SVasily Khoruzhick * SPI and LCD 82*f19eb154SVasily Khoruzhick */ 83*f19eb154SVasily Khoruzhick #ifdef CONFIG_CMD_SPI 84*f19eb154SVasily Khoruzhick #define CONFIG_SOFT_SPI 85*f19eb154SVasily Khoruzhick #define CONFIG_LCD 86*f19eb154SVasily Khoruzhick #define CONFIG_PXA_LCD 87*f19eb154SVasily Khoruzhick #define CONFIG_LMS283GF05 88*f19eb154SVasily Khoruzhick 89*f19eb154SVasily Khoruzhick #define SPI_DELAY udelay(10) 90*f19eb154SVasily Khoruzhick #define SPI_SDA(val) zipitz2_spi_sda(val) 91*f19eb154SVasily Khoruzhick #define SPI_SCL(val) zipitz2_spi_scl(val) 92*f19eb154SVasily Khoruzhick #define SPI_READ zipitz2_spi_read() 93*f19eb154SVasily Khoruzhick #ifndef __ASSEMBLY__ 94*f19eb154SVasily Khoruzhick void zipitz2_spi_sda(int); 95*f19eb154SVasily Khoruzhick void zipitz2_spi_scl(int); 96*f19eb154SVasily Khoruzhick unsigned char zipitz2_spi_read(void); 97*f19eb154SVasily Khoruzhick #endif 98*f19eb154SVasily Khoruzhick #endif 99*f19eb154SVasily Khoruzhick 100*f19eb154SVasily Khoruzhick /* 101*f19eb154SVasily Khoruzhick * HUSH Shell Configuration 102*f19eb154SVasily Khoruzhick */ 103*f19eb154SVasily Khoruzhick #define CONFIG_SYS_HUSH_PARSER 1 104*f19eb154SVasily Khoruzhick 105*f19eb154SVasily Khoruzhick #define CONFIG_SYS_LONGHELP /* undef to save memory */ 106*f19eb154SVasily Khoruzhick #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 107*f19eb154SVasily Khoruzhick #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 108*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 109*f19eb154SVasily Khoruzhick #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 110*f19eb154SVasily Khoruzhick #define CONFIG_SYS_DEVICE_NULLDEV 1 111*f19eb154SVasily Khoruzhick 112*f19eb154SVasily Khoruzhick /* 113*f19eb154SVasily Khoruzhick * Clock Configuration 114*f19eb154SVasily Khoruzhick */ 115*f19eb154SVasily Khoruzhick #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ 116*f19eb154SVasily Khoruzhick 117*f19eb154SVasily Khoruzhick /* 118*f19eb154SVasily Khoruzhick * SRAM Map 119*f19eb154SVasily Khoruzhick */ 120*f19eb154SVasily Khoruzhick #define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ 121*f19eb154SVasily Khoruzhick #define PHYS_SRAM_SIZE 0x00040000 /* 256k */ 122*f19eb154SVasily Khoruzhick 123*f19eb154SVasily Khoruzhick /* 124*f19eb154SVasily Khoruzhick * DRAM Map 125*f19eb154SVasily Khoruzhick */ 126*f19eb154SVasily Khoruzhick #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ 127*f19eb154SVasily Khoruzhick #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 128*f19eb154SVasily Khoruzhick #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 129*f19eb154SVasily Khoruzhick 130*f19eb154SVasily Khoruzhick #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ 131*f19eb154SVasily Khoruzhick #define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ 132*f19eb154SVasily Khoruzhick 133*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 134*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 135*f19eb154SVasily Khoruzhick 136*f19eb154SVasily Khoruzhick #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE 137*f19eb154SVasily Khoruzhick 138*f19eb154SVasily Khoruzhick #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 139*f19eb154SVasily Khoruzhick #define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) 140*f19eb154SVasily Khoruzhick 141*f19eb154SVasily Khoruzhick /* 142*f19eb154SVasily Khoruzhick * NOR FLASH 143*f19eb154SVasily Khoruzhick */ 144*f19eb154SVasily Khoruzhick #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 145*f19eb154SVasily Khoruzhick #define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ 146*f19eb154SVasily Khoruzhick #define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */ 147*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 148*f19eb154SVasily Khoruzhick 149*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_CFI 150*f19eb154SVasily Khoruzhick #define CONFIG_FLASH_CFI_DRIVER 1 151*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 152*f19eb154SVasily Khoruzhick 153*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 154*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 155*f19eb154SVasily Khoruzhick 156*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MAX_FLASH_BANKS 1 157*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MAX_FLASH_SECT 256 158*f19eb154SVasily Khoruzhick 159*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 160*f19eb154SVasily Khoruzhick 161*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 162*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 163*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_LOCK_TOUT 240000 164*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000 165*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_PROTECTION 166*f19eb154SVasily Khoruzhick 167*f19eb154SVasily Khoruzhick /* 168*f19eb154SVasily Khoruzhick * GPIO settings 169*f19eb154SVasily Khoruzhick */ 170*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR0_L_VAL 0x02000140 171*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR0_U_VAL 0x59188000 172*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR1_L_VAL 0x63900002 173*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950 174*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa 175*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR2_U_VAL 0x29000308 176*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR3_L_VAL 0x54000000 177*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR3_U_VAL 0x000000d5 178*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPCR0_VAL 0x00000000 179*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPCR1_VAL 0x00000020 180*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPCR2_VAL 0x00000000 181*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPCR3_VAL 0x00000000 182*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 183*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab 184*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff 185*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a 186*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPSR0_VAL 0x06080400 187*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPSR1_VAL 0x007f0000 188*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPSR2_VAL 0x032a0000 189*f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPSR3_VAL 0x00000180 190*f19eb154SVasily Khoruzhick 191*f19eb154SVasily Khoruzhick #define CONFIG_SYS_PSSR_VAL 0x30 192*f19eb154SVasily Khoruzhick 193*f19eb154SVasily Khoruzhick /* 194*f19eb154SVasily Khoruzhick * Clock settings 195*f19eb154SVasily Khoruzhick */ 196*f19eb154SVasily Khoruzhick #define CONFIG_SYS_CKEN 0x00511220 197*f19eb154SVasily Khoruzhick #define CONFIG_SYS_CCCR 0x00000190 198*f19eb154SVasily Khoruzhick 199*f19eb154SVasily Khoruzhick /* 200*f19eb154SVasily Khoruzhick * Memory settings 201*f19eb154SVasily Khoruzhick */ 202*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MSC0_VAL 0x2ffc38f8 203*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MSC1_VAL 0x0000ccd1 204*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MSC2_VAL 0x0000b884 205*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MDCNFG_VAL 0x08000ba9 206*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MDREFR_VAL 0x2011a01e 207*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MDMRS_VAL 0x00000000 208*f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 209*f19eb154SVasily Khoruzhick #define CONFIG_SYS_SXCNFG_VAL 0x40044004 210*f19eb154SVasily Khoruzhick 211*f19eb154SVasily Khoruzhick /* 212*f19eb154SVasily Khoruzhick * PCMCIA and CF Interfaces 213*f19eb154SVasily Khoruzhick */ 214*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MECR_VAL 0x00000001 215*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCMEM0_VAL 0x00014307 216*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCMEM1_VAL 0x00014307 217*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCATT0_VAL 0x0001c787 218*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCATT1_VAL 0x0001c787 219*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCIO0_VAL 0x0001430f 220*f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCIO1_VAL 0x0001430f 221*f19eb154SVasily Khoruzhick 222*f19eb154SVasily Khoruzhick #include "pxa-common.h" 223*f19eb154SVasily Khoruzhick 224*f19eb154SVasily Khoruzhick #endif /* __CONFIG_H */ 225