xref: /openbmc/u-boot/include/configs/zipitz2.h (revision 83d290c5)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2f19eb154SVasily Khoruzhick /*
3f19eb154SVasily Khoruzhick  * Aeronix Zipit Z2 configuration file
4f19eb154SVasily Khoruzhick  *
5f19eb154SVasily Khoruzhick  * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
6f19eb154SVasily Khoruzhick  */
7f19eb154SVasily Khoruzhick 
8f19eb154SVasily Khoruzhick #ifndef __CONFIG_H
9f19eb154SVasily Khoruzhick #define __CONFIG_H
10f19eb154SVasily Khoruzhick 
11f19eb154SVasily Khoruzhick /*
12f19eb154SVasily Khoruzhick  * High Level Board Configuration Options
13f19eb154SVasily Khoruzhick  */
14f19eb154SVasily Khoruzhick #define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
15f19eb154SVasily Khoruzhick 
16f19eb154SVasily Khoruzhick #undef	CONFIG_SKIP_LOWLEVEL_INIT
17f19eb154SVasily Khoruzhick #define	CONFIG_PREBOOT
18f19eb154SVasily Khoruzhick 
19f19eb154SVasily Khoruzhick /*
20f19eb154SVasily Khoruzhick  * Environment settings
21f19eb154SVasily Khoruzhick  */
22f19eb154SVasily Khoruzhick #define	CONFIG_ENV_OVERWRITE
23f19eb154SVasily Khoruzhick #define CONFIG_ENV_ADDR			0x40000
24f19eb154SVasily Khoruzhick #define CONFIG_ENV_SIZE			0x10000
25f19eb154SVasily Khoruzhick 
26f19eb154SVasily Khoruzhick #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
27f19eb154SVasily Khoruzhick #define	CONFIG_ARCH_CPU_INIT
28f19eb154SVasily Khoruzhick 
29f19eb154SVasily Khoruzhick #define	CONFIG_BOOTCOMMAND						\
30f19eb154SVasily Khoruzhick 	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
31f19eb154SVasily Khoruzhick 	"then "								\
32f19eb154SVasily Khoruzhick 		"source 0xa0000000; "					\
33f19eb154SVasily Khoruzhick 	"else "								\
34f19eb154SVasily Khoruzhick 		"bootm 0x50000; "					\
35f19eb154SVasily Khoruzhick 	"fi; "
36f19eb154SVasily Khoruzhick #define	CONFIG_TIMESTAMP
37f19eb154SVasily Khoruzhick #define	CONFIG_CMDLINE_TAG
38f19eb154SVasily Khoruzhick #define	CONFIG_SETUP_MEMORY_TAGS
39f19eb154SVasily Khoruzhick 
40f19eb154SVasily Khoruzhick /*
41f19eb154SVasily Khoruzhick  * Serial Console Configuration
42f19eb154SVasily Khoruzhick  * STUART - the lower serial port on Colibri board
43f19eb154SVasily Khoruzhick  */
44f19eb154SVasily Khoruzhick #define	CONFIG_STUART			1
45f19eb154SVasily Khoruzhick 
46f19eb154SVasily Khoruzhick /*
47f19eb154SVasily Khoruzhick  * Bootloader Components Configuration
48f19eb154SVasily Khoruzhick  */
49f19eb154SVasily Khoruzhick 
50f19eb154SVasily Khoruzhick /*
51f19eb154SVasily Khoruzhick  * MMC Card Configuration
52f19eb154SVasily Khoruzhick  */
53f19eb154SVasily Khoruzhick #ifdef	CONFIG_CMD_MMC
54f19eb154SVasily Khoruzhick #define	CONFIG_PXA_MMC_GENERIC
55f19eb154SVasily Khoruzhick #define	CONFIG_SYS_MMC_BASE		0xF0000000
56f19eb154SVasily Khoruzhick #endif
57f19eb154SVasily Khoruzhick 
58f19eb154SVasily Khoruzhick /*
59f19eb154SVasily Khoruzhick  * SPI and LCD
60f19eb154SVasily Khoruzhick  */
61f19eb154SVasily Khoruzhick #ifdef	CONFIG_CMD_SPI
62f19eb154SVasily Khoruzhick #define	CONFIG_SOFT_SPI
6359fa089bSVasily Khoruzhick #define	CONFIG_LCD_ROTATION
64f19eb154SVasily Khoruzhick #define	CONFIG_PXA_LCD
65f19eb154SVasily Khoruzhick #define	CONFIG_LMS283GF05
66f19eb154SVasily Khoruzhick 
67f19eb154SVasily Khoruzhick #define	SPI_DELAY	udelay(10)
68f19eb154SVasily Khoruzhick #define	SPI_SDA(val)	zipitz2_spi_sda(val)
69f19eb154SVasily Khoruzhick #define	SPI_SCL(val)	zipitz2_spi_scl(val)
70f19eb154SVasily Khoruzhick #define	SPI_READ	zipitz2_spi_read()
71f19eb154SVasily Khoruzhick #ifndef	__ASSEMBLY__
72f19eb154SVasily Khoruzhick void zipitz2_spi_sda(int);
73f19eb154SVasily Khoruzhick void zipitz2_spi_scl(int);
74f19eb154SVasily Khoruzhick unsigned char zipitz2_spi_read(void);
75f19eb154SVasily Khoruzhick #endif
76f19eb154SVasily Khoruzhick #endif
77f19eb154SVasily Khoruzhick 
78f19eb154SVasily Khoruzhick #define	CONFIG_SYS_DEVICE_NULLDEV	1
79f19eb154SVasily Khoruzhick 
80f19eb154SVasily Khoruzhick /*
81f19eb154SVasily Khoruzhick  * Clock Configuration
82f19eb154SVasily Khoruzhick  */
83f19eb154SVasily Khoruzhick #define CONFIG_SYS_CPUSPEED		0x190		/* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
84f19eb154SVasily Khoruzhick 
85f19eb154SVasily Khoruzhick /*
86f19eb154SVasily Khoruzhick  * SRAM Map
87f19eb154SVasily Khoruzhick  */
88f19eb154SVasily Khoruzhick #define	PHYS_SRAM			0x5c000000	/* SRAM Bank #1 */
89f19eb154SVasily Khoruzhick #define	PHYS_SRAM_SIZE			0x00040000	/* 256k */
90f19eb154SVasily Khoruzhick 
91f19eb154SVasily Khoruzhick /*
92f19eb154SVasily Khoruzhick  * DRAM Map
93f19eb154SVasily Khoruzhick  */
94f19eb154SVasily Khoruzhick #define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
95f19eb154SVasily Khoruzhick #define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
96f19eb154SVasily Khoruzhick #define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */
97f19eb154SVasily Khoruzhick 
98f19eb154SVasily Khoruzhick #define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
99f19eb154SVasily Khoruzhick #define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */
100f19eb154SVasily Khoruzhick 
101f19eb154SVasily Khoruzhick #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
102f19eb154SVasily Khoruzhick #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
103f19eb154SVasily Khoruzhick 
104f19eb154SVasily Khoruzhick #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
105f19eb154SVasily Khoruzhick 
106f19eb154SVasily Khoruzhick #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
107f19eb154SVasily Khoruzhick #define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
108f19eb154SVasily Khoruzhick 
109f19eb154SVasily Khoruzhick /*
110f19eb154SVasily Khoruzhick  * NOR FLASH
111f19eb154SVasily Khoruzhick  */
112f19eb154SVasily Khoruzhick #define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
113f19eb154SVasily Khoruzhick #define PHYS_FLASH_SIZE			0x00800000	/* 8 MB */
114f19eb154SVasily Khoruzhick #define PHYS_FLASH_SECT_SIZE		0x00010000	/* 64 KB sectors */
115f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
116f19eb154SVasily Khoruzhick 
117f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_CFI
118f19eb154SVasily Khoruzhick #define CONFIG_FLASH_CFI_DRIVER		1
119f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
120f19eb154SVasily Khoruzhick 
121f19eb154SVasily Khoruzhick #define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
122f19eb154SVasily Khoruzhick #define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
123f19eb154SVasily Khoruzhick 
124f19eb154SVasily Khoruzhick #define CONFIG_SYS_MAX_FLASH_BANKS	1
125f19eb154SVasily Khoruzhick #define CONFIG_SYS_MAX_FLASH_SECT	256
126f19eb154SVasily Khoruzhick 
127f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
128f19eb154SVasily Khoruzhick 
129f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_ERASE_TOUT	240000
130f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_WRITE_TOUT	240000
131f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_LOCK_TOUT	240000
132f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
133f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLASH_PROTECTION
134f19eb154SVasily Khoruzhick 
135f19eb154SVasily Khoruzhick /*
136f19eb154SVasily Khoruzhick  * GPIO settings
137f19eb154SVasily Khoruzhick  */
138f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR0_L_VAL	0x02000140
139f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR0_U_VAL	0x59188000
140f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR1_L_VAL	0x63900002
141f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR1_U_VAL	0xaaa03950
142f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR2_L_VAL	0x0aaaaaaa
143f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR2_U_VAL	0x29000308
144f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR3_L_VAL	0x54000000
145f19eb154SVasily Khoruzhick #define CONFIG_SYS_GAFR3_U_VAL	0x000000d5
146f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPCR0_VAL	0x00000000
147f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPCR1_VAL	0x00000020
148f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPCR2_VAL	0x00000000
149f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPCR3_VAL	0x00000000
150f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPDR0_VAL	0xdafcee00
151f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPDR1_VAL	0xffa3aaab
152f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPDR2_VAL	0x8fe9ffff
153f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPDR3_VAL	0x001b1f8a
154f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPSR0_VAL	0x06080400
155f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPSR1_VAL	0x007f0000
156f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPSR2_VAL	0x032a0000
157f19eb154SVasily Khoruzhick #define CONFIG_SYS_GPSR3_VAL	0x00000180
158f19eb154SVasily Khoruzhick 
159f19eb154SVasily Khoruzhick #define CONFIG_SYS_PSSR_VAL	0x30
160f19eb154SVasily Khoruzhick 
161f19eb154SVasily Khoruzhick /*
162f19eb154SVasily Khoruzhick  * Clock settings
163f19eb154SVasily Khoruzhick  */
164f19eb154SVasily Khoruzhick #define CONFIG_SYS_CKEN		0x00511220
165f19eb154SVasily Khoruzhick #define CONFIG_SYS_CCCR		0x00000190
166f19eb154SVasily Khoruzhick 
167f19eb154SVasily Khoruzhick /*
168f19eb154SVasily Khoruzhick  * Memory settings
169f19eb154SVasily Khoruzhick  */
170f19eb154SVasily Khoruzhick #define CONFIG_SYS_MSC0_VAL	0x2ffc38f8
171f19eb154SVasily Khoruzhick #define CONFIG_SYS_MSC1_VAL	0x0000ccd1
172f19eb154SVasily Khoruzhick #define CONFIG_SYS_MSC2_VAL	0x0000b884
173f19eb154SVasily Khoruzhick #define CONFIG_SYS_MDCNFG_VAL	0x08000ba9
174f19eb154SVasily Khoruzhick #define CONFIG_SYS_MDREFR_VAL	0x2011a01e
175f19eb154SVasily Khoruzhick #define CONFIG_SYS_MDMRS_VAL	0x00000000
176f19eb154SVasily Khoruzhick #define CONFIG_SYS_FLYCNFG_VAL	0x00010001
177f19eb154SVasily Khoruzhick #define CONFIG_SYS_SXCNFG_VAL	0x40044004
178f19eb154SVasily Khoruzhick 
179f19eb154SVasily Khoruzhick /*
180f19eb154SVasily Khoruzhick  * PCMCIA and CF Interfaces
181f19eb154SVasily Khoruzhick  */
182f19eb154SVasily Khoruzhick #define CONFIG_SYS_MECR_VAL	0x00000001
183f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCMEM0_VAL	0x00014307
184f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCMEM1_VAL	0x00014307
185f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCATT0_VAL	0x0001c787
186f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCATT1_VAL	0x0001c787
187f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCIO0_VAL	0x0001430f
188f19eb154SVasily Khoruzhick #define CONFIG_SYS_MCIO1_VAL	0x0001430f
189f19eb154SVasily Khoruzhick 
190f19eb154SVasily Khoruzhick #include "pxa-common.h"
191f19eb154SVasily Khoruzhick 
192f19eb154SVasily Khoruzhick #endif	/* __CONFIG_H */
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