1 /* 2 * Copyright (C) 2007-2013 Tensilica, Inc. 3 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include <asm/arch/core.h> 12 #include <asm/addrspace.h> 13 #include <asm/config.h> 14 15 /* 16 * The 'xtfpga' board describes a set of very similar boards with only minimal 17 * differences. 18 */ 19 20 /*=====================*/ 21 /* Board and Processor */ 22 /*=====================*/ 23 24 #define CONFIG_XTFPGA 25 26 /* FPGA CPU freq after init */ 27 #define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) 28 29 /*===================*/ 30 /* RAM Layout */ 31 /*===================*/ 32 33 #if XCHAL_HAVE_PTP_MMU 34 #define CONFIG_SYS_MEMORY_BASE \ 35 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) 36 #define CONFIG_SYS_IO_BASE 0xf0000000 37 #else 38 #define CONFIG_SYS_MEMORY_BASE 0x60000000 39 #define CONFIG_SYS_IO_BASE 0x90000000 40 #define CONFIG_MAX_MEM_MAPPED 0x10000000 41 #endif 42 43 /* Onboard RAM sizes: 44 * 45 * LX60 0x04000000 64 MB 46 * LX110 0x03000000 48 MB 47 * LX200 0x06000000 96 MB 48 * ML605 0x18000000 384 MB 49 * KC705 0x38000000 896 MB 50 * 51 * noMMU configurations can only see first 256MB of onboard memory. 52 */ 53 54 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 55 #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE 56 #else 57 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 58 #endif 59 60 #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) 61 62 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ 63 #ifdef CONFIG_XTFPGA_LX60 64 # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ 65 #else 66 # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ 67 #endif 68 69 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ 70 71 /* Linux boot param area in RAM (used only when booting linux) */ 72 #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) 73 74 /* Memory test is destructive so default must not overlap vectors or U-Boot*/ 75 #define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) 76 #define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) 77 78 /* Load address for stand-alone applications. 79 * MEMADDR cannot be used here, because the definition needs to be 80 * a plain number as it's used as -Ttext argument for ld in standalone 81 * example makefile. 82 * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. 83 */ 84 #if XCHAL_HAVE_PTP_MMU 85 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR 86 #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 87 #else 88 #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 89 #endif 90 #else 91 #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 92 #endif 93 94 #if defined(CONFIG_MAX_MEM_MAPPED) && \ 95 CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE 96 #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED 97 #else 98 #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE 99 #endif 100 101 #define CONFIG_SYS_MEMORY_TOP MEMADDR(CONFIG_SYS_MEMORY_SIZE) 102 #define CONFIG_SYS_TEXT_ADDR \ 103 (CONFIG_SYS_MEMORY_TOP - CONFIG_SYS_MONITOR_LEN) 104 105 /* Used by tftpboot; env var 'loadaddr' */ 106 #define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) 107 108 /*==============================*/ 109 /* U-Boot general configuration */ 110 /*==============================*/ 111 112 #define CONFIG_BOARD_POSTCLK_INIT 113 #define CONFIG_MISC_INIT_R 114 115 #define CONFIG_BOOTFILE "uImage" 116 /* Console I/O Buffer Size */ 117 #define CONFIG_SYS_CBSIZE 1024 118 /* Prt buf */ 119 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 120 sizeof(CONFIG_SYS_PROMPT) + 16) 121 /* max number of command args */ 122 #define CONFIG_SYS_MAXARGS 16 123 /* Boot Argument Buffer Size */ 124 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 125 126 /*=================*/ 127 /* U-Boot commands */ 128 /*=================*/ 129 130 #define CONFIG_CMD_SAVES 131 132 /*==============================*/ 133 /* U-Boot autoboot configuration */ 134 /*==============================*/ 135 136 #define CONFIG_BOOT_RETRY_TIME 60 /* retry after 60 secs */ 137 138 #define CONFIG_AUTO_COMPLETE /* Support tab autocompletion */ 139 #define CONFIG_CMDLINE_EDITING 140 #define CONFIG_SYS_LONGHELP 141 #define CONFIG_MX_CYCLIC 142 #define CONFIG_SHOW_BOOT_PROGRESS 143 144 #ifdef DEBUG 145 #define CONFIG_PANIC_HANG 1 /* Require manual reboot */ 146 #endif 147 148 149 /*=========================================*/ 150 /* FPGA Registers (board info and control) */ 151 /*=========================================*/ 152 153 /* 154 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier 155 * releases may not provide any/all of these registers or at these offsets. 156 * Some of the FPGA registers are broken down into bitfields described by 157 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. 158 */ 159 160 /* Date of FPGA bitstream build in binary coded decimal (BCD) */ 161 #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) 162 #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ 163 #define FPGAREG_MTH_WIDTH 8 164 #define FPGAREG_MTH_MASK 0xFF000000 165 #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ 166 #define FPGAREG_DAY_WIDTH 8 167 #define FPGAREG_DAY_MASK 0x00FF0000 168 #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ 169 #define FPGAREG_YEAR_WIDTH 16 170 #define FPGAREG_YEAR_MASK 0x0000FFFF 171 172 /* FPGA core clock frequency in Hz (also input to UART) */ 173 #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ 174 175 /* 176 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): 177 * Bits 0..5 set the lower 6 bits of the default ethernet MAC. 178 * Bit 6 is reserved for future use by Tensilica. 179 * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to 180 * the base of flash * (when on/1) or to the base of RAM (when off/0). 181 */ 182 #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) 183 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ 184 #define FPGAREG_MAC_WIDTH 6 185 #define FPGAREG_MAC_MASK 0x3f 186 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ 187 #define FPGAREG_BOOT_WIDTH 1 188 #define FPGAREG_BOOT_MASK 0x80 189 #define FPGAREG_BOOT_RAM 0 190 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) 191 192 /* Force hard reset of board by writing a code to this register */ 193 #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ 194 #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ 195 196 /*====================*/ 197 /* Serial Driver Info */ 198 /*====================*/ 199 200 #define CONFIG_SYS_NS16550_SERIAL 201 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 202 #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ 203 204 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ 205 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ 206 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 207 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 208 209 /*======================*/ 210 /* Ethernet Driver Info */ 211 /*======================*/ 212 213 #define CONFIG_ETHBASE 00:50:C2:13:6f:00 214 #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) 215 #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) 216 217 /*=====================*/ 218 /* Flash & Environment */ 219 /*=====================*/ 220 221 #define CONFIG_SYS_FLASH_CFI 222 #define CONFIG_FLASH_CFI_DRIVER /* use generic CFI driver */ 223 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 224 #define CONFIG_SYS_MAX_FLASH_BANKS 1 225 #ifdef CONFIG_XTFPGA_LX60 226 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ 227 # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ 228 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ 229 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 230 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 231 #elif defined(CONFIG_XTFPGA_KC705) 232 # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ 233 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 234 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 235 # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) 236 # define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000) 237 #else 238 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ 239 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 240 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 241 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 242 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 243 #endif 244 #define CONFIG_SYS_MAX_FLASH_SECT \ 245 (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \ 246 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1) 247 #define CONFIG_SYS_FLASH_PROTECTION /* hw flash protection */ 248 249 /* 250 * Put environment in top block (64kB) 251 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB 252 */ 253 #define CONFIG_ENV_IS_IN_FLASH 254 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ) 255 #define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ 256 257 /* print 'E' for empty sector on flinfo */ 258 #define CONFIG_SYS_FLASH_EMPTY_INFO 259 260 #endif /* __CONFIG_H */ 261