1 /* 2 * Copyright (C) 2007-2013 Tensilica, Inc. 3 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include <asm/arch/core.h> 12 #include <asm/addrspace.h> 13 #include <asm/config.h> 14 15 /* 16 * The 'xtfpga' board describes a set of very similar boards with only minimal 17 * differences. 18 */ 19 20 /*=====================*/ 21 /* Board and Processor */ 22 /*=====================*/ 23 24 #define CONFIG_XTFPGA 25 26 /* FPGA CPU freq after init */ 27 #define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) 28 29 /*===================*/ 30 /* RAM Layout */ 31 /*===================*/ 32 33 #if XCHAL_HAVE_PTP_MMU 34 #define CONFIG_SYS_MEMORY_BASE \ 35 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) 36 #define CONFIG_SYS_IO_BASE 0xf0000000 37 #else 38 #define CONFIG_SYS_MEMORY_BASE 0x60000000 39 #define CONFIG_SYS_IO_BASE 0x90000000 40 #define CONFIG_MAX_MEM_MAPPED 0x10000000 41 #endif 42 43 /* Onboard RAM sizes: 44 * 45 * LX60 0x04000000 64 MB 46 * LX110 0x03000000 48 MB 47 * LX200 0x06000000 96 MB 48 * ML605 0x18000000 384 MB 49 * KC705 0x38000000 896 MB 50 * 51 * noMMU configurations can only see first 256MB of onboard memory. 52 */ 53 54 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 55 #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE 56 #else 57 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 58 #endif 59 60 #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) 61 62 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ 63 #ifdef CONFIG_XTFPGA_LX60 64 # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ 65 #else 66 # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ 67 #endif 68 69 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ 70 71 /* Linux boot param area in RAM (used only when booting linux) */ 72 #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) 73 74 /* Memory test is destructive so default must not overlap vectors or U-Boot*/ 75 #define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) 76 #define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) 77 78 /* Load address for stand-alone applications. 79 * MEMADDR cannot be used here, because the definition needs to be 80 * a plain number as it's used as -Ttext argument for ld in standalone 81 * example makefile. 82 * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. 83 */ 84 #if XCHAL_HAVE_PTP_MMU 85 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR 86 #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 87 #else 88 #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 89 #endif 90 #else 91 #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 92 #endif 93 94 #if defined(CONFIG_MAX_MEM_MAPPED) && \ 95 CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE 96 #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED 97 #else 98 #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE 99 #endif 100 101 #define XTENSA_SYS_TEXT_ADDR \ 102 (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) 103 104 /* Used by tftpboot; env var 'loadaddr' */ 105 #define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) 106 107 /*==============================*/ 108 /* U-Boot general configuration */ 109 /*==============================*/ 110 111 #define CONFIG_BOARD_POSTCLK_INIT 112 #define CONFIG_MISC_INIT_R 113 114 #define CONFIG_BOOTFILE "uImage" 115 /* Console I/O Buffer Size */ 116 #define CONFIG_SYS_CBSIZE 1024 117 /* Boot Argument Buffer Size */ 118 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 119 120 /*==============================*/ 121 /* U-Boot autoboot configuration */ 122 /*==============================*/ 123 124 #define CONFIG_AUTO_COMPLETE /* Support tab autocompletion */ 125 #define CONFIG_CMDLINE_EDITING 126 #define CONFIG_SYS_LONGHELP 127 #define CONFIG_MX_CYCLIC 128 #define CONFIG_SHOW_BOOT_PROGRESS 129 130 131 /*=========================================*/ 132 /* FPGA Registers (board info and control) */ 133 /*=========================================*/ 134 135 /* 136 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier 137 * releases may not provide any/all of these registers or at these offsets. 138 * Some of the FPGA registers are broken down into bitfields described by 139 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. 140 */ 141 142 /* Date of FPGA bitstream build in binary coded decimal (BCD) */ 143 #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) 144 #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ 145 #define FPGAREG_MTH_WIDTH 8 146 #define FPGAREG_MTH_MASK 0xFF000000 147 #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ 148 #define FPGAREG_DAY_WIDTH 8 149 #define FPGAREG_DAY_MASK 0x00FF0000 150 #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ 151 #define FPGAREG_YEAR_WIDTH 16 152 #define FPGAREG_YEAR_MASK 0x0000FFFF 153 154 /* FPGA core clock frequency in Hz (also input to UART) */ 155 #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ 156 157 /* 158 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): 159 * Bits 0..5 set the lower 6 bits of the default ethernet MAC. 160 * Bit 6 is reserved for future use by Tensilica. 161 * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to 162 * the base of flash * (when on/1) or to the base of RAM (when off/0). 163 */ 164 #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) 165 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ 166 #define FPGAREG_MAC_WIDTH 6 167 #define FPGAREG_MAC_MASK 0x3f 168 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ 169 #define FPGAREG_BOOT_WIDTH 1 170 #define FPGAREG_BOOT_MASK 0x80 171 #define FPGAREG_BOOT_RAM 0 172 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) 173 174 /* Force hard reset of board by writing a code to this register */ 175 #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ 176 #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ 177 178 /*====================*/ 179 /* Serial Driver Info */ 180 /*====================*/ 181 182 #define CONFIG_SYS_NS16550_SERIAL 183 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 184 #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ 185 186 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ 187 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ 188 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 189 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 190 191 /*======================*/ 192 /* Ethernet Driver Info */ 193 /*======================*/ 194 195 #define CONFIG_ETHBASE 00:50:C2:13:6f:00 196 #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) 197 #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) 198 199 /*=====================*/ 200 /* Flash & Environment */ 201 /*=====================*/ 202 203 #define CONFIG_SYS_FLASH_CFI 204 #define CONFIG_FLASH_CFI_DRIVER /* use generic CFI driver */ 205 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 206 #define CONFIG_SYS_MAX_FLASH_BANKS 1 207 #ifdef CONFIG_XTFPGA_LX60 208 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ 209 # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */ 210 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ 211 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 212 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 213 #elif defined(CONFIG_XTFPGA_KC705) 214 # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ 215 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 216 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 217 # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) 218 # define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000) 219 #else 220 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ 221 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */ 222 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ 223 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) 224 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 225 #endif 226 #define CONFIG_SYS_MAX_FLASH_SECT \ 227 (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \ 228 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1) 229 #define CONFIG_SYS_FLASH_PROTECTION /* hw flash protection */ 230 231 /* 232 * Put environment in top block (64kB) 233 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB 234 */ 235 #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ) 236 #define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ 237 238 /* print 'E' for empty sector on flinfo */ 239 #define CONFIG_SYS_FLASH_EMPTY_INFO 240 241 #endif /* __CONFIG_H */ 242