xref: /openbmc/u-boot/include/configs/xpress.h (revision a7f480d9)
1*a7f480d9SStefan Roese /*
2*a7f480d9SStefan Roese  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
3*a7f480d9SStefan Roese  *
4*a7f480d9SStefan Roese  * Configuration settings for the CCV xPress board
5*a7f480d9SStefan Roese  *
6*a7f480d9SStefan Roese  * SPDX-License-Identifier:	GPL-2.0+
7*a7f480d9SStefan Roese  */
8*a7f480d9SStefan Roese #ifndef __XPRESS_CONFIG_H
9*a7f480d9SStefan Roese #define __XPRESS_CONFIG_H
10*a7f480d9SStefan Roese 
11*a7f480d9SStefan Roese #include "mx6_common.h"
12*a7f480d9SStefan Roese #include <asm/imx-common/gpio.h>
13*a7f480d9SStefan Roese 
14*a7f480d9SStefan Roese /* SPL options */
15*a7f480d9SStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT
16*a7f480d9SStefan Roese #define CONFIG_SPL_MMC_SUPPORT
17*a7f480d9SStefan Roese #include "imx6_spl.h"
18*a7f480d9SStefan Roese 
19*a7f480d9SStefan Roese #define CONFIG_DISPLAY_CPUINFO
20*a7f480d9SStefan Roese #define CONFIG_DISPLAY_BOARDINFO
21*a7f480d9SStefan Roese 
22*a7f480d9SStefan Roese /* Size of malloc() pool */
23*a7f480d9SStefan Roese #define CONFIG_SYS_MALLOC_LEN		(16 << 20)
24*a7f480d9SStefan Roese 
25*a7f480d9SStefan Roese #define CONFIG_BOARD_EARLY_INIT_F
26*a7f480d9SStefan Roese #define CONFIG_BOARD_LATE_INIT
27*a7f480d9SStefan Roese 
28*a7f480d9SStefan Roese #define CONFIG_MXC_UART
29*a7f480d9SStefan Roese #define CONFIG_MXC_UART_BASE		UART1_BASE
30*a7f480d9SStefan Roese 
31*a7f480d9SStefan Roese /* MMC Configs */
32*a7f480d9SStefan Roese #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
33*a7f480d9SStefan Roese #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
34*a7f480d9SStefan Roese 
35*a7f480d9SStefan Roese /* I2C configs */
36*a7f480d9SStefan Roese #define CONFIG_CMD_I2C
37*a7f480d9SStefan Roese #define CONFIG_SYS_I2C
38*a7f480d9SStefan Roese #define CONFIG_SYS_I2C_MXC
39*a7f480d9SStefan Roese #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
40*a7f480d9SStefan Roese #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
41*a7f480d9SStefan Roese #define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
42*a7f480d9SStefan Roese #define CONFIG_SYS_I2C_SPEED		100000
43*a7f480d9SStefan Roese 
44*a7f480d9SStefan Roese /* Miscellaneous configurable options */
45*a7f480d9SStefan Roese #define CONFIG_CMD_MEMTEST
46*a7f480d9SStefan Roese #define CONFIG_SYS_MEMTEST_START	0x80000000
47*a7f480d9SStefan Roese #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000000)
48*a7f480d9SStefan Roese 
49*a7f480d9SStefan Roese #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
50*a7f480d9SStefan Roese #define CONFIG_SYS_HZ			1000
51*a7f480d9SStefan Roese 
52*a7f480d9SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET
53*a7f480d9SStefan Roese #define CONFIG_CMDLINE_EDITING
54*a7f480d9SStefan Roese 
55*a7f480d9SStefan Roese /* Physical Memory Map */
56*a7f480d9SStefan Roese #define CONFIG_NR_DRAM_BANKS		1
57*a7f480d9SStefan Roese #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
58*a7f480d9SStefan Roese #define PHYS_SDRAM_SIZE			(128 << 20)
59*a7f480d9SStefan Roese 
60*a7f480d9SStefan Roese #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
61*a7f480d9SStefan Roese #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
62*a7f480d9SStefan Roese #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
63*a7f480d9SStefan Roese 
64*a7f480d9SStefan Roese #define CONFIG_SYS_INIT_SP_OFFSET \
65*a7f480d9SStefan Roese 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
66*a7f480d9SStefan Roese #define CONFIG_SYS_INIT_SP_ADDR \
67*a7f480d9SStefan Roese 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
68*a7f480d9SStefan Roese 
69*a7f480d9SStefan Roese /* FLASH and environment organization */
70*a7f480d9SStefan Roese #define CONFIG_SYS_NO_FLASH
71*a7f480d9SStefan Roese 
72*a7f480d9SStefan Roese /* Environment is in stored in the eMMC boot partition */
73*a7f480d9SStefan Roese #define CONFIG_ENV_SIZE			(16 << 10)
74*a7f480d9SStefan Roese #define CONFIG_ENV_IS_IN_MMC
75*a7f480d9SStefan Roese #define CONFIG_ENV_OFFSET		(512 << 10)
76*a7f480d9SStefan Roese #define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC2 */
77*a7f480d9SStefan Roese #define CONFIG_SYS_MMC_ENV_PART		1	/* boot parition */
78*a7f480d9SStefan Roese #define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC2 */
79*a7f480d9SStefan Roese 
80*a7f480d9SStefan Roese #define CONFIG_OF_LIBFDT
81*a7f480d9SStefan Roese #define CONFIG_CMD_BOOTZ
82*a7f480d9SStefan Roese #define CONFIG_CMD_BMODE
83*a7f480d9SStefan Roese #define CONFIG_CMD_CACHE
84*a7f480d9SStefan Roese 
85*a7f480d9SStefan Roese /* USB Configs */
86*a7f480d9SStefan Roese #define CONFIG_CMD_USB
87*a7f480d9SStefan Roese #define CONFIG_USB_EHCI
88*a7f480d9SStefan Roese #define CONFIG_USB_EHCI_MX6
89*a7f480d9SStefan Roese #define CONFIG_USB_STORAGE
90*a7f480d9SStefan Roese #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
91*a7f480d9SStefan Roese #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
92*a7f480d9SStefan Roese #define CONFIG_MXC_USB_FLAGS		0
93*a7f480d9SStefan Roese #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
94*a7f480d9SStefan Roese 
95*a7f480d9SStefan Roese #define CONFIG_FEC_MXC
96*a7f480d9SStefan Roese #define CONFIG_MII
97*a7f480d9SStefan Roese #define CONFIG_CMD_MII
98*a7f480d9SStefan Roese #define CONFIG_FEC_ENET_DEV		0
99*a7f480d9SStefan Roese #define IMX_FEC_BASE			ENET_BASE_ADDR
100*a7f480d9SStefan Roese #define CONFIG_FEC_MXC_PHYADDR          0x0
101*a7f480d9SStefan Roese #define CONFIG_FEC_XCV_TYPE             RMII
102*a7f480d9SStefan Roese #define CONFIG_ETHPRIME			"FEC"
103*a7f480d9SStefan Roese #define CONFIG_PHYLIB
104*a7f480d9SStefan Roese #define CONFIG_PHY_SMSC
105*a7f480d9SStefan Roese 
106*a7f480d9SStefan Roese #define CONFIG_IMX_THERMAL
107*a7f480d9SStefan Roese 
108*a7f480d9SStefan Roese #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
109*a7f480d9SStefan Roese 
110*a7f480d9SStefan Roese #define CONFIG_UBOOT_SECTOR_START	0x2
111*a7f480d9SStefan Roese #define CONFIG_UBOOT_SECTOR_COUNT	0x3fe
112*a7f480d9SStefan Roese 
113*a7f480d9SStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \
114*a7f480d9SStefan Roese 	"script=boot.scr\0" \
115*a7f480d9SStefan Roese 	"image=zImage\0" \
116*a7f480d9SStefan Roese 	"console=ttymxc0\0" \
117*a7f480d9SStefan Roese 	"fdt_high=0xffffffff\0" \
118*a7f480d9SStefan Roese 	"initrd_high=0xffffffff\0" \
119*a7f480d9SStefan Roese 	"fdt_file=undefined\0" \
120*a7f480d9SStefan Roese 	"fdt_addr=0x83000000\0" \
121*a7f480d9SStefan Roese 	"boot_fdt=try\0" \
122*a7f480d9SStefan Roese 	"ip_dyn=yes\0" \
123*a7f480d9SStefan Roese 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
124*a7f480d9SStefan Roese 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
125*a7f480d9SStefan Roese 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
126*a7f480d9SStefan Roese 	"mmcautodetect=yes\0" \
127*a7f480d9SStefan Roese 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
128*a7f480d9SStefan Roese 		"root=${mmcroot}\0" \
129*a7f480d9SStefan Roese 	"loadbootscript=" \
130*a7f480d9SStefan Roese 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
131*a7f480d9SStefan Roese 	"bootscript=echo Running bootscript from mmc ...; " \
132*a7f480d9SStefan Roese 		"source\0" \
133*a7f480d9SStefan Roese 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
134*a7f480d9SStefan Roese 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
135*a7f480d9SStefan Roese 	"mmcboot=echo Booting from mmc ...; " \
136*a7f480d9SStefan Roese 		"run mmcargs; " \
137*a7f480d9SStefan Roese 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
138*a7f480d9SStefan Roese 			"if run loadfdt; then " \
139*a7f480d9SStefan Roese 				"bootz ${loadaddr} - ${fdt_addr}; " \
140*a7f480d9SStefan Roese 			"else " \
141*a7f480d9SStefan Roese 				"if test ${boot_fdt} = try; then " \
142*a7f480d9SStefan Roese 					"bootz; " \
143*a7f480d9SStefan Roese 				"else " \
144*a7f480d9SStefan Roese 					"echo WARN: Cannot load the DT; " \
145*a7f480d9SStefan Roese 				"fi; " \
146*a7f480d9SStefan Roese 			"fi; " \
147*a7f480d9SStefan Roese 		"else " \
148*a7f480d9SStefan Roese 			"bootz; " \
149*a7f480d9SStefan Roese 		"fi;\0" \
150*a7f480d9SStefan Roese 	"uboot=ccv/u-boot.imx\0"					\
151*a7f480d9SStefan Roese 	"uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0"	\
152*a7f480d9SStefan Roese 	"uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0"		\
153*a7f480d9SStefan Roese 	"update_uboot=if tftp ${uboot}; then "				\
154*a7f480d9SStefan Roese 		"if itest ${filesize} > 0; then "			\
155*a7f480d9SStefan Roese 			"mmc dev 0 1;"					\
156*a7f480d9SStefan Roese 			"setexpr blkc ${filesize} / 0x200;"		\
157*a7f480d9SStefan Roese 			"setexpr blkc ${blkc} + 1;"			\
158*a7f480d9SStefan Roese 			"if itest ${blkc} <= ${uboot_size}; then "	\
159*a7f480d9SStefan Roese 				"mmc write ${loadaddr} ${uboot_start} "	\
160*a7f480d9SStefan Roese 					"${blkc};"			\
161*a7f480d9SStefan Roese 			"fi;"						\
162*a7f480d9SStefan Roese 		"fi; fi;"						\
163*a7f480d9SStefan Roese 		"setenv filesize; setenv blkc\0"			\
164*a7f480d9SStefan Roese 	"update_bootpart=mmc bootbus 0 2 1 2;mmc partconf 0 1 1 0\0"
165*a7f480d9SStefan Roese 
166*a7f480d9SStefan Roese #endif /* __XPRESS_CONFIG_H */
167