1 /* 2 * Copyright 2010 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite550x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_XPEDITE550X 1 18 #define CONFIG_SYS_BOARD_NAME "XPedite5500" 19 #define CONFIG_SYS_FORM_PMC_XMC 1 20 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ 21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 22 23 #ifndef CONFIG_SYS_TEXT_BASE 24 #define CONFIG_SYS_TEXT_BASE 0xfff80000 25 #endif 26 27 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 28 #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */ 29 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 30 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 33 #define CONFIG_FSL_ELBC 1 34 35 /* 36 * Multicore config 37 */ 38 #define CONFIG_MP 39 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 40 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 41 42 /* 43 * DDR config 44 */ 45 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 46 #define CONFIG_DDR_SPD 47 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 48 #define SPD_EEPROM_ADDRESS 0x54 49 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 50 #define CONFIG_NUM_DDR_CONTROLLERS 1 51 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 52 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 53 #define CONFIG_DDR_ECC 54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 56 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 57 #define CONFIG_VERY_BIG_RAM 58 59 #ifndef __ASSEMBLY__ 60 extern unsigned long get_board_sys_clk(unsigned long dummy); 61 extern unsigned long get_board_ddr_clk(unsigned long dummy); 62 #endif 63 64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 65 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 66 67 /* 68 * These can be toggled for performance analysis, otherwise use default. 69 */ 70 #define CONFIG_L2_CACHE /* toggle L2 cache */ 71 #define CONFIG_BTB /* toggle branch predition */ 72 #define CONFIG_ENABLE_36BIT_PHYS 1 73 74 #define CONFIG_SYS_CCSRBAR 0xef000000 75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 76 77 /* 78 * Diagnostics 79 */ 80 #define CONFIG_SYS_ALT_MEMTEST 81 #define CONFIG_SYS_MEMTEST_START 0x10000000 82 #define CONFIG_SYS_MEMTEST_END 0x20000000 83 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 84 CONFIG_SYS_POST_I2C) 85 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ 86 CONFIG_SYS_I2C_LM75_ADDR, \ 87 CONFIG_SYS_I2C_LM90_ADDR, \ 88 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 89 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 90 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 91 CONFIG_SYS_I2C_RTC_ADDR} 92 93 /* 94 * Memory map 95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 96 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 97 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 98 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 99 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 100 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 101 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 102 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 103 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 104 */ 105 106 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 107 108 /* 109 * NAND flash configuration 110 */ 111 #define CONFIG_SYS_NAND_BASE 0xef800000 112 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 113 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 114 CONFIG_SYS_NAND_BASE2} 115 #define CONFIG_SYS_MAX_NAND_DEVICE 2 116 #define CONFIG_NAND_FSL_ELBC 117 118 /* 119 * NOR flash configuration 120 */ 121 #define CONFIG_SYS_FLASH_BASE 0xf8000000 122 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 123 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 124 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 125 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 126 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 127 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 131 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 132 {0xf7f40000, 0xc0000} } 133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 134 135 /* 136 * Chip select configuration 137 */ 138 /* NOR Flash 0 on CS0 */ 139 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 140 BR_PS_16 | \ 141 BR_V) 142 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 143 OR_GPCM_CSNT | \ 144 OR_GPCM_XACS | \ 145 OR_GPCM_ACS_DIV2 | \ 146 OR_GPCM_SCY_8 | \ 147 OR_GPCM_TRLX | \ 148 OR_GPCM_EHTR | \ 149 OR_GPCM_EAD) 150 151 /* NOR Flash 1 on CS1 */ 152 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 153 BR_PS_16 | \ 154 BR_V) 155 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 156 157 /* NAND flash on CS2 */ 158 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 159 (2<<BR_DECC_SHIFT) | \ 160 BR_PS_8 | \ 161 BR_MS_FCM | \ 162 BR_V) 163 164 /* NAND flash on CS2 */ 165 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 166 OR_FCM_PGS | \ 167 OR_FCM_CSCT | \ 168 OR_FCM_CST | \ 169 OR_FCM_CHT | \ 170 OR_FCM_SCY_1 | \ 171 OR_FCM_TRLX | \ 172 OR_FCM_EHTR) 173 174 /* NAND flash on CS3 */ 175 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 176 (2<<BR_DECC_SHIFT) | \ 177 BR_PS_8 | \ 178 BR_MS_FCM | \ 179 BR_V) 180 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 181 182 /* 183 * Use L1 as initial stack 184 */ 185 #define CONFIG_SYS_INIT_RAM_LOCK 1 186 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 187 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 188 189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 191 192 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 193 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 194 195 /* 196 * Serial Port 197 */ 198 #define CONFIG_CONS_INDEX 1 199 #define CONFIG_SYS_NS16550_SERIAL 200 #define CONFIG_SYS_NS16550_REG_SIZE 1 201 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 202 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 203 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 204 #define CONFIG_SYS_BAUDRATE_TABLE \ 205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 206 #define CONFIG_BAUDRATE 115200 207 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 208 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 209 210 #define CONFIG_FDT_FIXUP_PCI_IRQ 1 211 212 /* 213 * I2C 214 */ 215 #define CONFIG_SYS_I2C 216 #define CONFIG_SYS_I2C_FSL 217 #define CONFIG_SYS_FSL_I2C_SPEED 400000 218 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 219 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 220 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 221 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 222 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 223 224 /* I2C DS7505 temperature sensor */ 225 #define CONFIG_DTT_LM75 226 #define CONFIG_DTT_SENSORS { 0 } 227 #define CONFIG_SYS_I2C_LM75_ADDR 0x48 228 229 /* I2C ADT7461 temperature sensor */ 230 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C 231 232 /* I2C EEPROM - AT24C128B */ 233 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 237 238 /* I2C RTC */ 239 #define CONFIG_RTC_M41T11 1 240 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 241 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 242 243 /* GPIO */ 244 #define CONFIG_PCA953X 245 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 246 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 247 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 248 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 249 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 250 251 /* 252 * GPIO pin definitions, PU = pulled high, PD = pulled low 253 */ 254 /* PCA9557 @ 0x18*/ 255 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 256 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ 257 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 258 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ 259 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 260 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ 261 262 /* PCA9557 @ 0x1e*/ 263 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ 264 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ 265 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ 266 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ 267 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ 268 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ 269 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ 270 271 /* PCA9557 @ 0x1f */ 272 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ 273 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ 274 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ 275 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ 276 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ 277 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ 278 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ 279 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ 280 281 /* 282 * General PCI 283 * Memory space is mapped 1-1, but I/O space must start from 0. 284 */ 285 286 /* controller 1 - PEX8112 or XMC, depending on build option */ 287 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 288 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 289 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 290 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 291 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 292 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 293 294 /* 295 * Networking options 296 */ 297 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 298 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 299 #define CONFIG_TSEC_TBI 300 #define CONFIG_MII 1 /* MII PHY management */ 301 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 302 #define CONFIG_ETHPRIME "eTSEC2" 303 304 /* 305 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 306 * 1000mbps SGMII link 307 */ 308 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 309 TBICR_PHY_RESET \ 310 | TBICR_FULL_DUPLEX \ 311 | TBICR_SPEED1_SET \ 312 ) 313 314 #define CONFIG_TSEC1 1 315 #define CONFIG_TSEC1_NAME "eTSEC1" 316 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 317 #define TSEC1_PHY_ADDR 1 318 #define TSEC1_PHYIDX 0 319 #define CONFIG_HAS_ETH0 320 321 #define CONFIG_TSEC2 1 322 #define CONFIG_TSEC2_NAME "eTSEC2" 323 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 324 #define TSEC2_PHY_ADDR 2 325 #define TSEC2_PHYIDX 0 326 #define CONFIG_HAS_ETH1 327 328 #define CONFIG_TSEC3 1 329 #define CONFIG_TSEC3_NAME "eTSEC3" 330 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 331 #define TSEC3_PHY_ADDR 3 332 #define TSEC3_PHYIDX 0 333 #define CONFIG_HAS_ETH2 334 335 /* 336 * USB 337 */ 338 #define CONFIG_USB_EHCI 339 #define CONFIG_USB_EHCI_FSL 340 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 341 #define CONFIG_DOS_PARTITION 342 343 /* 344 * Command configuration. 345 */ 346 #define CONFIG_CMD_DATE 347 #define CONFIG_CMD_DTT 348 #define CONFIG_CMD_EEPROM 349 #define CONFIG_CMD_JFFS2 350 #define CONFIG_CMD_NAND 351 #define CONFIG_CMD_PCA953X 352 #define CONFIG_CMD_PCA953X_INFO 353 #define CONFIG_CMD_PCI 354 #define CONFIG_CMD_PCI_ENUM 355 #define CONFIG_CMD_REGINFO 356 357 /* 358 * Miscellaneous configurable options 359 */ 360 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 361 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 362 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 363 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 364 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 365 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 366 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 367 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 368 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 369 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 370 #define CONFIG_PREBOOT /* enable preboot variable */ 371 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 372 373 /* 374 * For booting Linux, the board info and command line data 375 * have to be in the first 16 MB of memory, since this is 376 * the maximum mapped by the Linux kernel during initialization. 377 */ 378 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 379 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 380 381 /* 382 * Environment Configuration 383 */ 384 #define CONFIG_ENV_IS_IN_FLASH 1 385 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 386 #define CONFIG_ENV_SIZE 0x8000 387 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 388 389 /* 390 * Flash memory map: 391 * fff80000 - ffffffff Pri U-Boot (512 KB) 392 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 393 * fff00000 - fff3ffff Pri FDT (256KB) 394 * fef00000 - ffefffff Pri OS image (16MB) 395 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 396 * 397 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 398 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 399 * f7f00000 - f7f3ffff Sec FDT (256KB) 400 * f6f00000 - f7efffff Sec OS image (16MB) 401 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 402 */ 403 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 404 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 405 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 406 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 407 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 408 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 409 410 #define CONFIG_PROG_UBOOT1 \ 411 "$download_cmd $loadaddr $ubootfile; " \ 412 "if test $? -eq 0; then " \ 413 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 414 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 415 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 416 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 417 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 418 "if test $? -ne 0; then " \ 419 "echo PROGRAM FAILED; " \ 420 "else; " \ 421 "echo PROGRAM SUCCEEDED; " \ 422 "fi; " \ 423 "else; " \ 424 "echo DOWNLOAD FAILED; " \ 425 "fi;" 426 427 #define CONFIG_PROG_UBOOT2 \ 428 "$download_cmd $loadaddr $ubootfile; " \ 429 "if test $? -eq 0; then " \ 430 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 431 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 432 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 433 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 434 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 435 "if test $? -ne 0; then " \ 436 "echo PROGRAM FAILED; " \ 437 "else; " \ 438 "echo PROGRAM SUCCEEDED; " \ 439 "fi; " \ 440 "else; " \ 441 "echo DOWNLOAD FAILED; " \ 442 "fi;" 443 444 #define CONFIG_BOOT_OS_NET \ 445 "$download_cmd $osaddr $osfile; " \ 446 "if test $? -eq 0; then " \ 447 "if test -n $fdtaddr; then " \ 448 "$download_cmd $fdtaddr $fdtfile; " \ 449 "if test $? -eq 0; then " \ 450 "bootm $osaddr - $fdtaddr; " \ 451 "else; " \ 452 "echo FDT DOWNLOAD FAILED; " \ 453 "fi; " \ 454 "else; " \ 455 "bootm $osaddr; " \ 456 "fi; " \ 457 "else; " \ 458 "echo OS DOWNLOAD FAILED; " \ 459 "fi;" 460 461 #define CONFIG_PROG_OS1 \ 462 "$download_cmd $osaddr $osfile; " \ 463 "if test $? -eq 0; then " \ 464 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 465 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 466 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 467 "if test $? -ne 0; then " \ 468 "echo OS PROGRAM FAILED; " \ 469 "else; " \ 470 "echo OS PROGRAM SUCCEEDED; " \ 471 "fi; " \ 472 "else; " \ 473 "echo OS DOWNLOAD FAILED; " \ 474 "fi;" 475 476 #define CONFIG_PROG_OS2 \ 477 "$download_cmd $osaddr $osfile; " \ 478 "if test $? -eq 0; then " \ 479 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 480 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 481 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 482 "if test $? -ne 0; then " \ 483 "echo OS PROGRAM FAILED; " \ 484 "else; " \ 485 "echo OS PROGRAM SUCCEEDED; " \ 486 "fi; " \ 487 "else; " \ 488 "echo OS DOWNLOAD FAILED; " \ 489 "fi;" 490 491 #define CONFIG_PROG_FDT1 \ 492 "$download_cmd $fdtaddr $fdtfile; " \ 493 "if test $? -eq 0; then " \ 494 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 495 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 496 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 497 "if test $? -ne 0; then " \ 498 "echo FDT PROGRAM FAILED; " \ 499 "else; " \ 500 "echo FDT PROGRAM SUCCEEDED; " \ 501 "fi; " \ 502 "else; " \ 503 "echo FDT DOWNLOAD FAILED; " \ 504 "fi;" 505 506 #define CONFIG_PROG_FDT2 \ 507 "$download_cmd $fdtaddr $fdtfile; " \ 508 "if test $? -eq 0; then " \ 509 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 510 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 511 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 512 "if test $? -ne 0; then " \ 513 "echo FDT PROGRAM FAILED; " \ 514 "else; " \ 515 "echo FDT PROGRAM SUCCEEDED; " \ 516 "fi; " \ 517 "else; " \ 518 "echo FDT DOWNLOAD FAILED; " \ 519 "fi;" 520 521 #define CONFIG_EXTRA_ENV_SETTINGS \ 522 "autoload=yes\0" \ 523 "download_cmd=tftp\0" \ 524 "console_args=console=ttyS0,115200\0" \ 525 "root_args=root=/dev/nfs rw\0" \ 526 "misc_args=ip=on\0" \ 527 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 528 "bootfile=/home/user/file\0" \ 529 "osfile=/home/user/board.uImage\0" \ 530 "fdtfile=/home/user/board.dtb\0" \ 531 "ubootfile=/home/user/u-boot.bin\0" \ 532 "fdtaddr=0x1e00000\0" \ 533 "osaddr=0x1000000\0" \ 534 "loadaddr=0x1000000\0" \ 535 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 536 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 537 "prog_os1="CONFIG_PROG_OS1"\0" \ 538 "prog_os2="CONFIG_PROG_OS2"\0" \ 539 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 540 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 541 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 542 "bootcmd_flash1=run set_bootargs; " \ 543 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 544 "bootcmd_flash2=run set_bootargs; " \ 545 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 546 "bootcmd=run bootcmd_flash1\0" 547 #endif /* __CONFIG_H */ 548