1 /* 2 * Copyright 2010 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite550x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_SYS_BOARD_NAME "XPedite5500" 18 #define CONFIG_SYS_FORM_PMC_XMC 1 19 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ 20 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 21 22 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 23 #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */ 24 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 25 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 26 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 27 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 28 29 /* 30 * Multicore config 31 */ 32 #define CONFIG_MP 33 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 34 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 35 36 /* 37 * DDR config 38 */ 39 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 40 #define CONFIG_DDR_SPD 41 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 42 #define SPD_EEPROM_ADDRESS 0x54 43 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 44 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 45 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 46 #define CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 50 #define CONFIG_VERY_BIG_RAM 51 52 #ifndef __ASSEMBLY__ 53 extern unsigned long get_board_sys_clk(unsigned long dummy); 54 extern unsigned long get_board_ddr_clk(unsigned long dummy); 55 #endif 56 57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 58 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_L2_CACHE /* toggle L2 cache */ 64 #define CONFIG_BTB /* toggle branch predition */ 65 #define CONFIG_ENABLE_36BIT_PHYS 1 66 67 #define CONFIG_SYS_CCSRBAR 0xef000000 68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 69 70 /* 71 * Diagnostics 72 */ 73 #define CONFIG_SYS_ALT_MEMTEST 74 #define CONFIG_SYS_MEMTEST_START 0x10000000 75 #define CONFIG_SYS_MEMTEST_END 0x20000000 76 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 77 CONFIG_SYS_POST_I2C) 78 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ 79 CONFIG_SYS_I2C_LM75_ADDR, \ 80 CONFIG_SYS_I2C_LM90_ADDR, \ 81 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 82 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 83 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 84 CONFIG_SYS_I2C_RTC_ADDR} 85 86 /* 87 * Memory map 88 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 89 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 90 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 91 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 92 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 93 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 94 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 95 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 96 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 97 */ 98 99 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 100 101 /* 102 * NAND flash configuration 103 */ 104 #define CONFIG_SYS_NAND_BASE 0xef800000 105 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 106 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 107 CONFIG_SYS_NAND_BASE2} 108 #define CONFIG_SYS_MAX_NAND_DEVICE 2 109 #define CONFIG_NAND_FSL_ELBC 110 111 /* 112 * NOR flash configuration 113 */ 114 #define CONFIG_SYS_FLASH_BASE 0xf8000000 115 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 116 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 117 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 119 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 121 #define CONFIG_FLASH_CFI_DRIVER 122 #define CONFIG_SYS_FLASH_CFI 123 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 124 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 125 {0xf7f40000, 0xc0000} } 126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 127 128 /* 129 * Chip select configuration 130 */ 131 /* NOR Flash 0 on CS0 */ 132 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 133 BR_PS_16 | \ 134 BR_V) 135 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 136 OR_GPCM_CSNT | \ 137 OR_GPCM_XACS | \ 138 OR_GPCM_ACS_DIV2 | \ 139 OR_GPCM_SCY_8 | \ 140 OR_GPCM_TRLX | \ 141 OR_GPCM_EHTR | \ 142 OR_GPCM_EAD) 143 144 /* NOR Flash 1 on CS1 */ 145 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 146 BR_PS_16 | \ 147 BR_V) 148 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 149 150 /* NAND flash on CS2 */ 151 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 152 (2<<BR_DECC_SHIFT) | \ 153 BR_PS_8 | \ 154 BR_MS_FCM | \ 155 BR_V) 156 157 /* NAND flash on CS2 */ 158 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 159 OR_FCM_PGS | \ 160 OR_FCM_CSCT | \ 161 OR_FCM_CST | \ 162 OR_FCM_CHT | \ 163 OR_FCM_SCY_1 | \ 164 OR_FCM_TRLX | \ 165 OR_FCM_EHTR) 166 167 /* NAND flash on CS3 */ 168 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 169 (2<<BR_DECC_SHIFT) | \ 170 BR_PS_8 | \ 171 BR_MS_FCM | \ 172 BR_V) 173 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 174 175 /* 176 * Use L1 as initial stack 177 */ 178 #define CONFIG_SYS_INIT_RAM_LOCK 1 179 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 180 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 181 182 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 183 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 184 185 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 186 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 187 188 /* 189 * Serial Port 190 */ 191 #define CONFIG_CONS_INDEX 1 192 #define CONFIG_SYS_NS16550_SERIAL 193 #define CONFIG_SYS_NS16550_REG_SIZE 1 194 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 195 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 196 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 197 #define CONFIG_SYS_BAUDRATE_TABLE \ 198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 199 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 200 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 201 202 203 /* 204 * I2C 205 */ 206 #define CONFIG_SYS_I2C 207 #define CONFIG_SYS_I2C_FSL 208 #define CONFIG_SYS_FSL_I2C_SPEED 400000 209 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 211 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 212 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 213 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 214 215 /* I2C DS7505 temperature sensor */ 216 #define CONFIG_SYS_I2C_LM75_ADDR 0x48 217 218 /* I2C ADT7461 temperature sensor */ 219 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C 220 221 /* I2C EEPROM - AT24C128B */ 222 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 226 227 /* I2C RTC */ 228 #define CONFIG_RTC_M41T11 1 229 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 230 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 231 232 /* GPIO */ 233 #define CONFIG_PCA953X 234 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 235 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 236 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 237 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 238 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 239 240 /* 241 * GPIO pin definitions, PU = pulled high, PD = pulled low 242 */ 243 /* PCA9557 @ 0x18*/ 244 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 245 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ 246 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 247 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ 248 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 249 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ 250 251 /* PCA9557 @ 0x1e*/ 252 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ 253 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ 254 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ 255 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ 256 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ 257 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ 258 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ 259 260 /* PCA9557 @ 0x1f */ 261 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ 262 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ 263 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ 264 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ 265 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ 266 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ 267 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ 268 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ 269 270 /* 271 * General PCI 272 * Memory space is mapped 1-1, but I/O space must start from 0. 273 */ 274 275 /* controller 1 - PEX8112 or XMC, depending on build option */ 276 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 277 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 278 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 279 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 280 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 281 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 282 283 /* 284 * Networking options 285 */ 286 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 287 #define CONFIG_TSEC_TBI 288 #define CONFIG_MII 1 /* MII PHY management */ 289 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 290 #define CONFIG_ETHPRIME "eTSEC2" 291 292 /* 293 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 294 * 1000mbps SGMII link 295 */ 296 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 297 TBICR_PHY_RESET \ 298 | TBICR_FULL_DUPLEX \ 299 | TBICR_SPEED1_SET \ 300 ) 301 302 #define CONFIG_TSEC1 1 303 #define CONFIG_TSEC1_NAME "eTSEC1" 304 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 305 #define TSEC1_PHY_ADDR 1 306 #define TSEC1_PHYIDX 0 307 #define CONFIG_HAS_ETH0 308 309 #define CONFIG_TSEC2 1 310 #define CONFIG_TSEC2_NAME "eTSEC2" 311 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 312 #define TSEC2_PHY_ADDR 2 313 #define TSEC2_PHYIDX 0 314 #define CONFIG_HAS_ETH1 315 316 #define CONFIG_TSEC3 1 317 #define CONFIG_TSEC3_NAME "eTSEC3" 318 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 319 #define TSEC3_PHY_ADDR 3 320 #define TSEC3_PHYIDX 0 321 #define CONFIG_HAS_ETH2 322 323 /* 324 * USB 325 */ 326 #define CONFIG_USB_EHCI_FSL 327 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 328 329 /* 330 * Miscellaneous configurable options 331 */ 332 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 333 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 334 #define CONFIG_PREBOOT /* enable preboot variable */ 335 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 336 337 /* 338 * For booting Linux, the board info and command line data 339 * have to be in the first 16 MB of memory, since this is 340 * the maximum mapped by the Linux kernel during initialization. 341 */ 342 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 343 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 344 345 /* 346 * Environment Configuration 347 */ 348 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 349 #define CONFIG_ENV_SIZE 0x8000 350 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 351 352 /* 353 * Flash memory map: 354 * fff80000 - ffffffff Pri U-Boot (512 KB) 355 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 356 * fff00000 - fff3ffff Pri FDT (256KB) 357 * fef00000 - ffefffff Pri OS image (16MB) 358 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 359 * 360 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 361 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 362 * f7f00000 - f7f3ffff Sec FDT (256KB) 363 * f6f00000 - f7efffff Sec OS image (16MB) 364 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 365 */ 366 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 367 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 368 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 369 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 370 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 371 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 372 373 #define CONFIG_PROG_UBOOT1 \ 374 "$download_cmd $loadaddr $ubootfile; " \ 375 "if test $? -eq 0; then " \ 376 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 377 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 378 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 379 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 380 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 381 "if test $? -ne 0; then " \ 382 "echo PROGRAM FAILED; " \ 383 "else; " \ 384 "echo PROGRAM SUCCEEDED; " \ 385 "fi; " \ 386 "else; " \ 387 "echo DOWNLOAD FAILED; " \ 388 "fi;" 389 390 #define CONFIG_PROG_UBOOT2 \ 391 "$download_cmd $loadaddr $ubootfile; " \ 392 "if test $? -eq 0; then " \ 393 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 394 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 395 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 396 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 397 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 398 "if test $? -ne 0; then " \ 399 "echo PROGRAM FAILED; " \ 400 "else; " \ 401 "echo PROGRAM SUCCEEDED; " \ 402 "fi; " \ 403 "else; " \ 404 "echo DOWNLOAD FAILED; " \ 405 "fi;" 406 407 #define CONFIG_BOOT_OS_NET \ 408 "$download_cmd $osaddr $osfile; " \ 409 "if test $? -eq 0; then " \ 410 "if test -n $fdtaddr; then " \ 411 "$download_cmd $fdtaddr $fdtfile; " \ 412 "if test $? -eq 0; then " \ 413 "bootm $osaddr - $fdtaddr; " \ 414 "else; " \ 415 "echo FDT DOWNLOAD FAILED; " \ 416 "fi; " \ 417 "else; " \ 418 "bootm $osaddr; " \ 419 "fi; " \ 420 "else; " \ 421 "echo OS DOWNLOAD FAILED; " \ 422 "fi;" 423 424 #define CONFIG_PROG_OS1 \ 425 "$download_cmd $osaddr $osfile; " \ 426 "if test $? -eq 0; then " \ 427 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 428 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 429 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 430 "if test $? -ne 0; then " \ 431 "echo OS PROGRAM FAILED; " \ 432 "else; " \ 433 "echo OS PROGRAM SUCCEEDED; " \ 434 "fi; " \ 435 "else; " \ 436 "echo OS DOWNLOAD FAILED; " \ 437 "fi;" 438 439 #define CONFIG_PROG_OS2 \ 440 "$download_cmd $osaddr $osfile; " \ 441 "if test $? -eq 0; then " \ 442 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 443 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 444 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 445 "if test $? -ne 0; then " \ 446 "echo OS PROGRAM FAILED; " \ 447 "else; " \ 448 "echo OS PROGRAM SUCCEEDED; " \ 449 "fi; " \ 450 "else; " \ 451 "echo OS DOWNLOAD FAILED; " \ 452 "fi;" 453 454 #define CONFIG_PROG_FDT1 \ 455 "$download_cmd $fdtaddr $fdtfile; " \ 456 "if test $? -eq 0; then " \ 457 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 458 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 459 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 460 "if test $? -ne 0; then " \ 461 "echo FDT PROGRAM FAILED; " \ 462 "else; " \ 463 "echo FDT PROGRAM SUCCEEDED; " \ 464 "fi; " \ 465 "else; " \ 466 "echo FDT DOWNLOAD FAILED; " \ 467 "fi;" 468 469 #define CONFIG_PROG_FDT2 \ 470 "$download_cmd $fdtaddr $fdtfile; " \ 471 "if test $? -eq 0; then " \ 472 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 473 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 474 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 475 "if test $? -ne 0; then " \ 476 "echo FDT PROGRAM FAILED; " \ 477 "else; " \ 478 "echo FDT PROGRAM SUCCEEDED; " \ 479 "fi; " \ 480 "else; " \ 481 "echo FDT DOWNLOAD FAILED; " \ 482 "fi;" 483 484 #define CONFIG_EXTRA_ENV_SETTINGS \ 485 "autoload=yes\0" \ 486 "download_cmd=tftp\0" \ 487 "console_args=console=ttyS0,115200\0" \ 488 "root_args=root=/dev/nfs rw\0" \ 489 "misc_args=ip=on\0" \ 490 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 491 "bootfile=/home/user/file\0" \ 492 "osfile=/home/user/board.uImage\0" \ 493 "fdtfile=/home/user/board.dtb\0" \ 494 "ubootfile=/home/user/u-boot.bin\0" \ 495 "fdtaddr=0x1e00000\0" \ 496 "osaddr=0x1000000\0" \ 497 "loadaddr=0x1000000\0" \ 498 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 499 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 500 "prog_os1="CONFIG_PROG_OS1"\0" \ 501 "prog_os2="CONFIG_PROG_OS2"\0" \ 502 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 503 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 504 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 505 "bootcmd_flash1=run set_bootargs; " \ 506 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 507 "bootcmd_flash2=run set_bootargs; " \ 508 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 509 "bootcmd=run bootcmd_flash1\0" 510 #endif /* __CONFIG_H */ 511