1 /* 2 * Copyright 2010 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite550x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_XPEDITE550X 1 20 #define CONFIG_SYS_BOARD_NAME "XPedite5500" 21 #define CONFIG_SYS_FORM_PMC_XMC 1 22 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ 23 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 24 25 #ifndef CONFIG_SYS_TEXT_BASE 26 #define CONFIG_SYS_TEXT_BASE 0xfff80000 27 #endif 28 29 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 30 #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */ 31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 35 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 36 #define CONFIG_FSL_ELBC 1 37 38 /* 39 * Multicore config 40 */ 41 #define CONFIG_MP 42 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 43 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 44 45 /* 46 * DDR config 47 */ 48 #define CONFIG_SYS_FSL_DDR3 49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 50 #define CONFIG_DDR_SPD 51 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 52 #define SPD_EEPROM_ADDRESS 0x54 53 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 54 #define CONFIG_NUM_DDR_CONTROLLERS 1 55 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 56 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 57 #define CONFIG_DDR_ECC 58 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 59 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 61 #define CONFIG_VERY_BIG_RAM 62 63 #ifndef __ASSEMBLY__ 64 extern unsigned long get_board_sys_clk(unsigned long dummy); 65 extern unsigned long get_board_ddr_clk(unsigned long dummy); 66 #endif 67 68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 69 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 70 71 /* 72 * These can be toggled for performance analysis, otherwise use default. 73 */ 74 #define CONFIG_L2_CACHE /* toggle L2 cache */ 75 #define CONFIG_BTB /* toggle branch predition */ 76 #define CONFIG_ENABLE_36BIT_PHYS 1 77 78 #define CONFIG_SYS_CCSRBAR 0xef000000 79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 80 81 /* 82 * Diagnostics 83 */ 84 #define CONFIG_SYS_ALT_MEMTEST 85 #define CONFIG_SYS_MEMTEST_START 0x10000000 86 #define CONFIG_SYS_MEMTEST_END 0x20000000 87 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 88 CONFIG_SYS_POST_I2C) 89 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ 90 CONFIG_SYS_I2C_LM75_ADDR, \ 91 CONFIG_SYS_I2C_LM90_ADDR, \ 92 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 93 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 94 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 95 CONFIG_SYS_I2C_RTC_ADDR} 96 97 /* 98 * Memory map 99 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 100 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 101 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 102 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 103 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 104 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 105 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 106 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 107 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 108 */ 109 110 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 111 112 /* 113 * NAND flash configuration 114 */ 115 #define CONFIG_SYS_NAND_BASE 0xef800000 116 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 117 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 118 CONFIG_SYS_NAND_BASE2} 119 #define CONFIG_SYS_MAX_NAND_DEVICE 2 120 #define CONFIG_NAND_FSL_ELBC 121 122 /* 123 * NOR flash configuration 124 */ 125 #define CONFIG_SYS_FLASH_BASE 0xf8000000 126 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 127 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 128 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 129 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 130 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 131 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 132 #define CONFIG_FLASH_CFI_DRIVER 133 #define CONFIG_SYS_FLASH_CFI 134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 135 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 136 {0xf7f40000, 0xc0000} } 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 138 139 /* 140 * Chip select configuration 141 */ 142 /* NOR Flash 0 on CS0 */ 143 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 144 BR_PS_16 | \ 145 BR_V) 146 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 147 OR_GPCM_CSNT | \ 148 OR_GPCM_XACS | \ 149 OR_GPCM_ACS_DIV2 | \ 150 OR_GPCM_SCY_8 | \ 151 OR_GPCM_TRLX | \ 152 OR_GPCM_EHTR | \ 153 OR_GPCM_EAD) 154 155 /* NOR Flash 1 on CS1 */ 156 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 157 BR_PS_16 | \ 158 BR_V) 159 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 160 161 /* NAND flash on CS2 */ 162 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 163 (2<<BR_DECC_SHIFT) | \ 164 BR_PS_8 | \ 165 BR_MS_FCM | \ 166 BR_V) 167 168 /* NAND flash on CS2 */ 169 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 170 OR_FCM_PGS | \ 171 OR_FCM_CSCT | \ 172 OR_FCM_CST | \ 173 OR_FCM_CHT | \ 174 OR_FCM_SCY_1 | \ 175 OR_FCM_TRLX | \ 176 OR_FCM_EHTR) 177 178 /* NAND flash on CS3 */ 179 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 180 (2<<BR_DECC_SHIFT) | \ 181 BR_PS_8 | \ 182 BR_MS_FCM | \ 183 BR_V) 184 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 185 186 /* 187 * Use L1 as initial stack 188 */ 189 #define CONFIG_SYS_INIT_RAM_LOCK 1 190 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 191 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 192 193 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 194 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 195 196 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 197 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 198 199 /* 200 * Serial Port 201 */ 202 #define CONFIG_CONS_INDEX 1 203 #define CONFIG_SYS_NS16550_SERIAL 204 #define CONFIG_SYS_NS16550_REG_SIZE 1 205 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 206 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 207 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 208 #define CONFIG_SYS_BAUDRATE_TABLE \ 209 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 210 #define CONFIG_BAUDRATE 115200 211 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 212 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 213 214 #define CONFIG_FDT_FIXUP_PCI_IRQ 1 215 216 /* 217 * I2C 218 */ 219 #define CONFIG_SYS_I2C 220 #define CONFIG_SYS_I2C_FSL 221 #define CONFIG_SYS_FSL_I2C_SPEED 400000 222 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 223 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 224 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 225 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 226 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 227 228 /* I2C DS7505 temperature sensor */ 229 #define CONFIG_DTT_LM75 230 #define CONFIG_DTT_SENSORS { 0 } 231 #define CONFIG_SYS_I2C_LM75_ADDR 0x48 232 233 /* I2C ADT7461 temperature sensor */ 234 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C 235 236 /* I2C EEPROM - AT24C128B */ 237 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 238 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 241 242 /* I2C RTC */ 243 #define CONFIG_RTC_M41T11 1 244 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 245 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 246 247 /* GPIO */ 248 #define CONFIG_PCA953X 249 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 250 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 251 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 252 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 253 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 254 255 /* 256 * GPIO pin definitions, PU = pulled high, PD = pulled low 257 */ 258 /* PCA9557 @ 0x18*/ 259 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 260 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ 261 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 262 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ 263 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 264 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ 265 266 /* PCA9557 @ 0x1e*/ 267 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ 268 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ 269 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ 270 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ 271 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ 272 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ 273 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ 274 275 /* PCA9557 @ 0x1f */ 276 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ 277 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ 278 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ 279 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ 280 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ 281 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ 282 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ 283 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ 284 285 /* 286 * General PCI 287 * Memory space is mapped 1-1, but I/O space must start from 0. 288 */ 289 290 /* controller 1 - PEX8112 or XMC, depending on build option */ 291 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 292 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 293 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 294 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 295 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 296 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 297 298 /* 299 * Networking options 300 */ 301 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 302 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 303 #define CONFIG_TSEC_TBI 304 #define CONFIG_MII 1 /* MII PHY management */ 305 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 306 #define CONFIG_ETHPRIME "eTSEC2" 307 308 /* 309 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 310 * 1000mbps SGMII link 311 */ 312 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 313 TBICR_PHY_RESET \ 314 | TBICR_FULL_DUPLEX \ 315 | TBICR_SPEED1_SET \ 316 ) 317 318 #define CONFIG_TSEC1 1 319 #define CONFIG_TSEC1_NAME "eTSEC1" 320 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 321 #define TSEC1_PHY_ADDR 1 322 #define TSEC1_PHYIDX 0 323 #define CONFIG_HAS_ETH0 324 325 #define CONFIG_TSEC2 1 326 #define CONFIG_TSEC2_NAME "eTSEC2" 327 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 328 #define TSEC2_PHY_ADDR 2 329 #define TSEC2_PHYIDX 0 330 #define CONFIG_HAS_ETH1 331 332 #define CONFIG_TSEC3 1 333 #define CONFIG_TSEC3_NAME "eTSEC3" 334 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 335 #define TSEC3_PHY_ADDR 3 336 #define TSEC3_PHYIDX 0 337 #define CONFIG_HAS_ETH2 338 339 /* 340 * USB 341 */ 342 #define CONFIG_USB_EHCI 343 #define CONFIG_USB_EHCI_FSL 344 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 345 #define CONFIG_DOS_PARTITION 346 347 /* 348 * Command configuration. 349 */ 350 #define CONFIG_CMD_DATE 351 #define CONFIG_CMD_DTT 352 #define CONFIG_CMD_EEPROM 353 #define CONFIG_CMD_JFFS2 354 #define CONFIG_CMD_NAND 355 #define CONFIG_CMD_PCA953X 356 #define CONFIG_CMD_PCA953X_INFO 357 #define CONFIG_CMD_PCI 358 #define CONFIG_CMD_PCI_ENUM 359 #define CONFIG_CMD_REGINFO 360 361 /* 362 * Miscellaneous configurable options 363 */ 364 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 365 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 366 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 367 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 368 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 369 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 370 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 371 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 372 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 373 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 374 #define CONFIG_PREBOOT /* enable preboot variable */ 375 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 376 377 /* 378 * For booting Linux, the board info and command line data 379 * have to be in the first 16 MB of memory, since this is 380 * the maximum mapped by the Linux kernel during initialization. 381 */ 382 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 383 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 384 385 /* 386 * Environment Configuration 387 */ 388 #define CONFIG_ENV_IS_IN_FLASH 1 389 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 390 #define CONFIG_ENV_SIZE 0x8000 391 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 392 393 /* 394 * Flash memory map: 395 * fff80000 - ffffffff Pri U-Boot (512 KB) 396 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 397 * fff00000 - fff3ffff Pri FDT (256KB) 398 * fef00000 - ffefffff Pri OS image (16MB) 399 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 400 * 401 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 402 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 403 * f7f00000 - f7f3ffff Sec FDT (256KB) 404 * f6f00000 - f7efffff Sec OS image (16MB) 405 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 406 */ 407 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 408 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 409 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 410 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 411 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 412 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 413 414 #define CONFIG_PROG_UBOOT1 \ 415 "$download_cmd $loadaddr $ubootfile; " \ 416 "if test $? -eq 0; then " \ 417 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 418 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 419 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 420 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 421 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 422 "if test $? -ne 0; then " \ 423 "echo PROGRAM FAILED; " \ 424 "else; " \ 425 "echo PROGRAM SUCCEEDED; " \ 426 "fi; " \ 427 "else; " \ 428 "echo DOWNLOAD FAILED; " \ 429 "fi;" 430 431 #define CONFIG_PROG_UBOOT2 \ 432 "$download_cmd $loadaddr $ubootfile; " \ 433 "if test $? -eq 0; then " \ 434 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 435 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 436 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 437 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 438 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 439 "if test $? -ne 0; then " \ 440 "echo PROGRAM FAILED; " \ 441 "else; " \ 442 "echo PROGRAM SUCCEEDED; " \ 443 "fi; " \ 444 "else; " \ 445 "echo DOWNLOAD FAILED; " \ 446 "fi;" 447 448 #define CONFIG_BOOT_OS_NET \ 449 "$download_cmd $osaddr $osfile; " \ 450 "if test $? -eq 0; then " \ 451 "if test -n $fdtaddr; then " \ 452 "$download_cmd $fdtaddr $fdtfile; " \ 453 "if test $? -eq 0; then " \ 454 "bootm $osaddr - $fdtaddr; " \ 455 "else; " \ 456 "echo FDT DOWNLOAD FAILED; " \ 457 "fi; " \ 458 "else; " \ 459 "bootm $osaddr; " \ 460 "fi; " \ 461 "else; " \ 462 "echo OS DOWNLOAD FAILED; " \ 463 "fi;" 464 465 #define CONFIG_PROG_OS1 \ 466 "$download_cmd $osaddr $osfile; " \ 467 "if test $? -eq 0; then " \ 468 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 469 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 470 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 471 "if test $? -ne 0; then " \ 472 "echo OS PROGRAM FAILED; " \ 473 "else; " \ 474 "echo OS PROGRAM SUCCEEDED; " \ 475 "fi; " \ 476 "else; " \ 477 "echo OS DOWNLOAD FAILED; " \ 478 "fi;" 479 480 #define CONFIG_PROG_OS2 \ 481 "$download_cmd $osaddr $osfile; " \ 482 "if test $? -eq 0; then " \ 483 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 484 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 485 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 486 "if test $? -ne 0; then " \ 487 "echo OS PROGRAM FAILED; " \ 488 "else; " \ 489 "echo OS PROGRAM SUCCEEDED; " \ 490 "fi; " \ 491 "else; " \ 492 "echo OS DOWNLOAD FAILED; " \ 493 "fi;" 494 495 #define CONFIG_PROG_FDT1 \ 496 "$download_cmd $fdtaddr $fdtfile; " \ 497 "if test $? -eq 0; then " \ 498 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 499 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 500 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 501 "if test $? -ne 0; then " \ 502 "echo FDT PROGRAM FAILED; " \ 503 "else; " \ 504 "echo FDT PROGRAM SUCCEEDED; " \ 505 "fi; " \ 506 "else; " \ 507 "echo FDT DOWNLOAD FAILED; " \ 508 "fi;" 509 510 #define CONFIG_PROG_FDT2 \ 511 "$download_cmd $fdtaddr $fdtfile; " \ 512 "if test $? -eq 0; then " \ 513 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 514 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 515 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 516 "if test $? -ne 0; then " \ 517 "echo FDT PROGRAM FAILED; " \ 518 "else; " \ 519 "echo FDT PROGRAM SUCCEEDED; " \ 520 "fi; " \ 521 "else; " \ 522 "echo FDT DOWNLOAD FAILED; " \ 523 "fi;" 524 525 #define CONFIG_EXTRA_ENV_SETTINGS \ 526 "autoload=yes\0" \ 527 "download_cmd=tftp\0" \ 528 "console_args=console=ttyS0,115200\0" \ 529 "root_args=root=/dev/nfs rw\0" \ 530 "misc_args=ip=on\0" \ 531 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 532 "bootfile=/home/user/file\0" \ 533 "osfile=/home/user/board.uImage\0" \ 534 "fdtfile=/home/user/board.dtb\0" \ 535 "ubootfile=/home/user/u-boot.bin\0" \ 536 "fdtaddr=0x1e00000\0" \ 537 "osaddr=0x1000000\0" \ 538 "loadaddr=0x1000000\0" \ 539 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 540 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 541 "prog_os1="CONFIG_PROG_OS1"\0" \ 542 "prog_os2="CONFIG_PROG_OS2"\0" \ 543 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 544 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 545 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 546 "bootcmd_flash1=run set_bootargs; " \ 547 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 548 "bootcmd_flash2=run set_bootargs; " \ 549 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 550 "bootcmd=run bootcmd_flash1\0" 551 #endif /* __CONFIG_H */ 552