1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010 Extreme Engineering Solutions, Inc. 4 * Copyright 2007-2008 Freescale Semiconductor, Inc. 5 */ 6 7 /* 8 * xpedite550x board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_SYS_BOARD_NAME "XPedite5500" 17 #define CONFIG_SYS_FORM_PMC_XMC 1 18 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ 19 20 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 21 #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */ 22 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 23 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 25 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 26 27 /* 28 * Multicore config 29 */ 30 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 31 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 32 33 /* 34 * DDR config 35 */ 36 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 37 #define CONFIG_DDR_SPD 38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 39 #define SPD_EEPROM_ADDRESS 0x54 40 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 41 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 42 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 43 #define CONFIG_DDR_ECC 44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 47 #define CONFIG_VERY_BIG_RAM 48 49 #ifndef __ASSEMBLY__ 50 extern unsigned long get_board_sys_clk(unsigned long dummy); 51 extern unsigned long get_board_ddr_clk(unsigned long dummy); 52 #endif 53 54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 56 57 /* 58 * These can be toggled for performance analysis, otherwise use default. 59 */ 60 #define CONFIG_L2_CACHE /* toggle L2 cache */ 61 #define CONFIG_BTB /* toggle branch predition */ 62 #define CONFIG_ENABLE_36BIT_PHYS 1 63 64 #define CONFIG_SYS_CCSRBAR 0xef000000 65 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 66 67 /* 68 * Diagnostics 69 */ 70 #define CONFIG_SYS_MEMTEST_START 0x10000000 71 #define CONFIG_SYS_MEMTEST_END 0x20000000 72 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 73 CONFIG_SYS_POST_I2C) 74 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ 75 CONFIG_SYS_I2C_LM75_ADDR, \ 76 CONFIG_SYS_I2C_LM90_ADDR, \ 77 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 78 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 79 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 80 CONFIG_SYS_I2C_RTC_ADDR} 81 82 /* 83 * Memory map 84 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 85 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 86 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 87 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 88 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 89 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 90 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 91 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 92 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 93 */ 94 95 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 96 97 /* 98 * NAND flash configuration 99 */ 100 #define CONFIG_SYS_NAND_BASE 0xef800000 101 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 102 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 103 CONFIG_SYS_NAND_BASE2} 104 #define CONFIG_SYS_MAX_NAND_DEVICE 2 105 #define CONFIG_NAND_FSL_ELBC 106 107 /* 108 * NOR flash configuration 109 */ 110 #define CONFIG_SYS_FLASH_BASE 0xf8000000 111 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 112 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 113 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 114 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 115 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 116 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 117 #define CONFIG_FLASH_CFI_DRIVER 118 #define CONFIG_SYS_FLASH_CFI 119 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 120 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 121 {0xf7f40000, 0xc0000} } 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 123 124 /* 125 * Chip select configuration 126 */ 127 /* NOR Flash 0 on CS0 */ 128 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 129 BR_PS_16 | \ 130 BR_V) 131 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 132 OR_GPCM_CSNT | \ 133 OR_GPCM_XACS | \ 134 OR_GPCM_ACS_DIV2 | \ 135 OR_GPCM_SCY_8 | \ 136 OR_GPCM_TRLX | \ 137 OR_GPCM_EHTR | \ 138 OR_GPCM_EAD) 139 140 /* NOR Flash 1 on CS1 */ 141 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 142 BR_PS_16 | \ 143 BR_V) 144 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 145 146 /* NAND flash on CS2 */ 147 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 148 (2<<BR_DECC_SHIFT) | \ 149 BR_PS_8 | \ 150 BR_MS_FCM | \ 151 BR_V) 152 153 /* NAND flash on CS2 */ 154 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 155 OR_FCM_PGS | \ 156 OR_FCM_CSCT | \ 157 OR_FCM_CST | \ 158 OR_FCM_CHT | \ 159 OR_FCM_SCY_1 | \ 160 OR_FCM_TRLX | \ 161 OR_FCM_EHTR) 162 163 /* NAND flash on CS3 */ 164 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 165 (2<<BR_DECC_SHIFT) | \ 166 BR_PS_8 | \ 167 BR_MS_FCM | \ 168 BR_V) 169 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 170 171 /* 172 * Use L1 as initial stack 173 */ 174 #define CONFIG_SYS_INIT_RAM_LOCK 1 175 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 176 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 177 178 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 180 181 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 182 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 183 184 /* 185 * Serial Port 186 */ 187 #define CONFIG_SYS_NS16550_SERIAL 188 #define CONFIG_SYS_NS16550_REG_SIZE 1 189 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 190 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 191 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 192 #define CONFIG_SYS_BAUDRATE_TABLE \ 193 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 194 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 195 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 196 197 198 /* 199 * I2C 200 */ 201 #define CONFIG_SYS_I2C 202 #define CONFIG_SYS_I2C_FSL 203 #define CONFIG_SYS_FSL_I2C_SPEED 400000 204 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 205 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 206 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 207 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 208 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 209 210 /* I2C DS7505 temperature sensor */ 211 #define CONFIG_SYS_I2C_LM75_ADDR 0x48 212 213 /* I2C ADT7461 temperature sensor */ 214 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C 215 216 /* I2C EEPROM - AT24C128B */ 217 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 221 222 /* I2C RTC */ 223 #define CONFIG_RTC_M41T11 1 224 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 225 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 226 227 /* GPIO */ 228 #define CONFIG_PCA953X 229 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 230 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 231 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 232 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 233 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 234 235 /* 236 * GPIO pin definitions, PU = pulled high, PD = pulled low 237 */ 238 /* PCA9557 @ 0x18*/ 239 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 240 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ 241 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 242 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ 243 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 244 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ 245 246 /* PCA9557 @ 0x1e*/ 247 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ 248 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ 249 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ 250 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ 251 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ 252 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ 253 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ 254 255 /* PCA9557 @ 0x1f */ 256 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ 257 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ 258 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ 259 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ 260 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ 261 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ 262 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ 263 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ 264 265 /* 266 * General PCI 267 * Memory space is mapped 1-1, but I/O space must start from 0. 268 */ 269 270 /* controller 1 - PEX8112 or XMC, depending on build option */ 271 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 272 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 273 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 274 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 275 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 276 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 277 278 /* 279 * Networking options 280 */ 281 #define CONFIG_TSEC_TBI 282 #define CONFIG_MII 1 /* MII PHY management */ 283 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 284 #define CONFIG_ETHPRIME "eTSEC2" 285 286 /* 287 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 288 * 1000mbps SGMII link 289 */ 290 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 291 TBICR_PHY_RESET \ 292 | TBICR_FULL_DUPLEX \ 293 | TBICR_SPEED1_SET \ 294 ) 295 296 #define CONFIG_TSEC1 1 297 #define CONFIG_TSEC1_NAME "eTSEC1" 298 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 299 #define TSEC1_PHY_ADDR 1 300 #define TSEC1_PHYIDX 0 301 #define CONFIG_HAS_ETH0 302 303 #define CONFIG_TSEC2 1 304 #define CONFIG_TSEC2_NAME "eTSEC2" 305 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 306 #define TSEC2_PHY_ADDR 2 307 #define TSEC2_PHYIDX 0 308 #define CONFIG_HAS_ETH1 309 310 #define CONFIG_TSEC3 1 311 #define CONFIG_TSEC3_NAME "eTSEC3" 312 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 313 #define TSEC3_PHY_ADDR 3 314 #define TSEC3_PHYIDX 0 315 #define CONFIG_HAS_ETH2 316 317 /* 318 * USB 319 */ 320 #define CONFIG_USB_EHCI_FSL 321 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 322 323 /* 324 * Miscellaneous configurable options 325 */ 326 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 327 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 328 #define CONFIG_PREBOOT /* enable preboot variable */ 329 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 330 331 /* 332 * For booting Linux, the board info and command line data 333 * have to be in the first 16 MB of memory, since this is 334 * the maximum mapped by the Linux kernel during initialization. 335 */ 336 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 337 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 338 339 /* 340 * Environment Configuration 341 */ 342 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 343 #define CONFIG_ENV_SIZE 0x8000 344 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 345 346 /* 347 * Flash memory map: 348 * fff80000 - ffffffff Pri U-Boot (512 KB) 349 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 350 * fff00000 - fff3ffff Pri FDT (256KB) 351 * fef00000 - ffefffff Pri OS image (16MB) 352 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 353 * 354 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 355 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 356 * f7f00000 - f7f3ffff Sec FDT (256KB) 357 * f6f00000 - f7efffff Sec OS image (16MB) 358 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 359 */ 360 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 361 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 362 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 363 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 364 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 365 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 366 367 #define CONFIG_PROG_UBOOT1 \ 368 "$download_cmd $loadaddr $ubootfile; " \ 369 "if test $? -eq 0; then " \ 370 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 371 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 372 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 373 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 374 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 375 "if test $? -ne 0; then " \ 376 "echo PROGRAM FAILED; " \ 377 "else; " \ 378 "echo PROGRAM SUCCEEDED; " \ 379 "fi; " \ 380 "else; " \ 381 "echo DOWNLOAD FAILED; " \ 382 "fi;" 383 384 #define CONFIG_PROG_UBOOT2 \ 385 "$download_cmd $loadaddr $ubootfile; " \ 386 "if test $? -eq 0; then " \ 387 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 388 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 389 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 390 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 391 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 392 "if test $? -ne 0; then " \ 393 "echo PROGRAM FAILED; " \ 394 "else; " \ 395 "echo PROGRAM SUCCEEDED; " \ 396 "fi; " \ 397 "else; " \ 398 "echo DOWNLOAD FAILED; " \ 399 "fi;" 400 401 #define CONFIG_BOOT_OS_NET \ 402 "$download_cmd $osaddr $osfile; " \ 403 "if test $? -eq 0; then " \ 404 "if test -n $fdtaddr; then " \ 405 "$download_cmd $fdtaddr $fdtfile; " \ 406 "if test $? -eq 0; then " \ 407 "bootm $osaddr - $fdtaddr; " \ 408 "else; " \ 409 "echo FDT DOWNLOAD FAILED; " \ 410 "fi; " \ 411 "else; " \ 412 "bootm $osaddr; " \ 413 "fi; " \ 414 "else; " \ 415 "echo OS DOWNLOAD FAILED; " \ 416 "fi;" 417 418 #define CONFIG_PROG_OS1 \ 419 "$download_cmd $osaddr $osfile; " \ 420 "if test $? -eq 0; then " \ 421 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 422 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 423 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 424 "if test $? -ne 0; then " \ 425 "echo OS PROGRAM FAILED; " \ 426 "else; " \ 427 "echo OS PROGRAM SUCCEEDED; " \ 428 "fi; " \ 429 "else; " \ 430 "echo OS DOWNLOAD FAILED; " \ 431 "fi;" 432 433 #define CONFIG_PROG_OS2 \ 434 "$download_cmd $osaddr $osfile; " \ 435 "if test $? -eq 0; then " \ 436 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 437 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 438 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 439 "if test $? -ne 0; then " \ 440 "echo OS PROGRAM FAILED; " \ 441 "else; " \ 442 "echo OS PROGRAM SUCCEEDED; " \ 443 "fi; " \ 444 "else; " \ 445 "echo OS DOWNLOAD FAILED; " \ 446 "fi;" 447 448 #define CONFIG_PROG_FDT1 \ 449 "$download_cmd $fdtaddr $fdtfile; " \ 450 "if test $? -eq 0; then " \ 451 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 452 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 453 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 454 "if test $? -ne 0; then " \ 455 "echo FDT PROGRAM FAILED; " \ 456 "else; " \ 457 "echo FDT PROGRAM SUCCEEDED; " \ 458 "fi; " \ 459 "else; " \ 460 "echo FDT DOWNLOAD FAILED; " \ 461 "fi;" 462 463 #define CONFIG_PROG_FDT2 \ 464 "$download_cmd $fdtaddr $fdtfile; " \ 465 "if test $? -eq 0; then " \ 466 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 467 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 468 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 469 "if test $? -ne 0; then " \ 470 "echo FDT PROGRAM FAILED; " \ 471 "else; " \ 472 "echo FDT PROGRAM SUCCEEDED; " \ 473 "fi; " \ 474 "else; " \ 475 "echo FDT DOWNLOAD FAILED; " \ 476 "fi;" 477 478 #define CONFIG_EXTRA_ENV_SETTINGS \ 479 "autoload=yes\0" \ 480 "download_cmd=tftp\0" \ 481 "console_args=console=ttyS0,115200\0" \ 482 "root_args=root=/dev/nfs rw\0" \ 483 "misc_args=ip=on\0" \ 484 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 485 "bootfile=/home/user/file\0" \ 486 "osfile=/home/user/board.uImage\0" \ 487 "fdtfile=/home/user/board.dtb\0" \ 488 "ubootfile=/home/user/u-boot.bin\0" \ 489 "fdtaddr=0x1e00000\0" \ 490 "osaddr=0x1000000\0" \ 491 "loadaddr=0x1000000\0" \ 492 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 493 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 494 "prog_os1="CONFIG_PROG_OS1"\0" \ 495 "prog_os2="CONFIG_PROG_OS2"\0" \ 496 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 497 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 498 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 499 "bootcmd_flash1=run set_bootargs; " \ 500 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 501 "bootcmd_flash2=run set_bootargs; " \ 502 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 503 "bootcmd=run bootcmd_flash1\0" 504 #endif /* __CONFIG_H */ 505