1 /* 2 * Copyright 2010 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite550x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_XPEDITE550X 1 20 #define CONFIG_SYS_BOARD_NAME "XPedite5500" 21 #define CONFIG_SYS_FORM_PMC_XMC 1 22 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ 23 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 24 25 #ifndef CONFIG_SYS_TEXT_BASE 26 #define CONFIG_SYS_TEXT_BASE 0xfff80000 27 #endif 28 29 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 30 #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */ 31 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 32 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 35 #define CONFIG_FSL_ELBC 1 36 37 /* 38 * Multicore config 39 */ 40 #define CONFIG_MP 41 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 42 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 43 44 /* 45 * DDR config 46 */ 47 #define CONFIG_SYS_FSL_DDR3 48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 49 #define CONFIG_DDR_SPD 50 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 51 #define SPD_EEPROM_ADDRESS 0x54 52 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 53 #define CONFIG_NUM_DDR_CONTROLLERS 1 54 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 55 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 56 #define CONFIG_DDR_ECC 57 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 58 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 59 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 60 #define CONFIG_VERY_BIG_RAM 61 62 #ifndef __ASSEMBLY__ 63 extern unsigned long get_board_sys_clk(unsigned long dummy); 64 extern unsigned long get_board_ddr_clk(unsigned long dummy); 65 #endif 66 67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 68 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 69 70 /* 71 * These can be toggled for performance analysis, otherwise use default. 72 */ 73 #define CONFIG_L2_CACHE /* toggle L2 cache */ 74 #define CONFIG_BTB /* toggle branch predition */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_SYS_CCSRBAR 0xef000000 78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 79 80 /* 81 * Diagnostics 82 */ 83 #define CONFIG_SYS_ALT_MEMTEST 84 #define CONFIG_SYS_MEMTEST_START 0x10000000 85 #define CONFIG_SYS_MEMTEST_END 0x20000000 86 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 87 CONFIG_SYS_POST_I2C) 88 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ 89 CONFIG_SYS_I2C_LM75_ADDR, \ 90 CONFIG_SYS_I2C_LM90_ADDR, \ 91 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 92 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 93 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 94 CONFIG_SYS_I2C_RTC_ADDR} 95 96 /* 97 * Memory map 98 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 99 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 100 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 101 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 102 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 103 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 104 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 105 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 106 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 107 */ 108 109 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 110 111 /* 112 * NAND flash configuration 113 */ 114 #define CONFIG_SYS_NAND_BASE 0xef800000 115 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 116 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 117 CONFIG_SYS_NAND_BASE2} 118 #define CONFIG_SYS_MAX_NAND_DEVICE 2 119 #define CONFIG_NAND_FSL_ELBC 120 121 /* 122 * NOR flash configuration 123 */ 124 #define CONFIG_SYS_FLASH_BASE 0xf8000000 125 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 126 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 127 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 128 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 129 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 130 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 131 #define CONFIG_FLASH_CFI_DRIVER 132 #define CONFIG_SYS_FLASH_CFI 133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 134 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 135 {0xf7f40000, 0xc0000} } 136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 137 138 /* 139 * Chip select configuration 140 */ 141 /* NOR Flash 0 on CS0 */ 142 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 143 BR_PS_16 | \ 144 BR_V) 145 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 146 OR_GPCM_CSNT | \ 147 OR_GPCM_XACS | \ 148 OR_GPCM_ACS_DIV2 | \ 149 OR_GPCM_SCY_8 | \ 150 OR_GPCM_TRLX | \ 151 OR_GPCM_EHTR | \ 152 OR_GPCM_EAD) 153 154 /* NOR Flash 1 on CS1 */ 155 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 156 BR_PS_16 | \ 157 BR_V) 158 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 159 160 /* NAND flash on CS2 */ 161 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 162 (2<<BR_DECC_SHIFT) | \ 163 BR_PS_8 | \ 164 BR_MS_FCM | \ 165 BR_V) 166 167 /* NAND flash on CS2 */ 168 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 169 OR_FCM_PGS | \ 170 OR_FCM_CSCT | \ 171 OR_FCM_CST | \ 172 OR_FCM_CHT | \ 173 OR_FCM_SCY_1 | \ 174 OR_FCM_TRLX | \ 175 OR_FCM_EHTR) 176 177 /* NAND flash on CS3 */ 178 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 179 (2<<BR_DECC_SHIFT) | \ 180 BR_PS_8 | \ 181 BR_MS_FCM | \ 182 BR_V) 183 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 184 185 /* 186 * Use L1 as initial stack 187 */ 188 #define CONFIG_SYS_INIT_RAM_LOCK 1 189 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 190 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 191 192 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 193 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 194 195 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 196 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 197 198 /* 199 * Serial Port 200 */ 201 #define CONFIG_CONS_INDEX 1 202 #define CONFIG_SYS_NS16550_SERIAL 203 #define CONFIG_SYS_NS16550_REG_SIZE 1 204 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 207 #define CONFIG_SYS_BAUDRATE_TABLE \ 208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 209 #define CONFIG_BAUDRATE 115200 210 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 211 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 212 213 #define CONFIG_FDT_FIXUP_PCI_IRQ 1 214 215 /* 216 * I2C 217 */ 218 #define CONFIG_SYS_I2C 219 #define CONFIG_SYS_I2C_FSL 220 #define CONFIG_SYS_FSL_I2C_SPEED 400000 221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 222 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 223 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 224 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 225 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 226 227 /* I2C DS7505 temperature sensor */ 228 #define CONFIG_DTT_LM75 229 #define CONFIG_DTT_SENSORS { 0 } 230 #define CONFIG_SYS_I2C_LM75_ADDR 0x48 231 232 /* I2C ADT7461 temperature sensor */ 233 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C 234 235 /* I2C EEPROM - AT24C128B */ 236 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 237 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 240 241 /* I2C RTC */ 242 #define CONFIG_RTC_M41T11 1 243 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 244 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 245 246 /* GPIO */ 247 #define CONFIG_PCA953X 248 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 249 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 250 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 251 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 252 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 253 254 /* 255 * GPIO pin definitions, PU = pulled high, PD = pulled low 256 */ 257 /* PCA9557 @ 0x18*/ 258 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 259 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ 260 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 261 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ 262 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 263 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ 264 265 /* PCA9557 @ 0x1e*/ 266 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ 267 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ 268 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ 269 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ 270 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ 271 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ 272 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ 273 274 /* PCA9557 @ 0x1f */ 275 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ 276 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ 277 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ 278 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ 279 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ 280 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ 281 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ 282 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ 283 284 /* 285 * General PCI 286 * Memory space is mapped 1-1, but I/O space must start from 0. 287 */ 288 289 /* controller 1 - PEX8112 or XMC, depending on build option */ 290 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 291 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 292 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 293 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 294 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 295 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 296 297 /* 298 * Networking options 299 */ 300 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 301 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 302 #define CONFIG_TSEC_TBI 303 #define CONFIG_MII 1 /* MII PHY management */ 304 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 305 #define CONFIG_ETHPRIME "eTSEC2" 306 307 /* 308 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 309 * 1000mbps SGMII link 310 */ 311 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 312 TBICR_PHY_RESET \ 313 | TBICR_FULL_DUPLEX \ 314 | TBICR_SPEED1_SET \ 315 ) 316 317 #define CONFIG_TSEC1 1 318 #define CONFIG_TSEC1_NAME "eTSEC1" 319 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 320 #define TSEC1_PHY_ADDR 1 321 #define TSEC1_PHYIDX 0 322 #define CONFIG_HAS_ETH0 323 324 #define CONFIG_TSEC2 1 325 #define CONFIG_TSEC2_NAME "eTSEC2" 326 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 327 #define TSEC2_PHY_ADDR 2 328 #define TSEC2_PHYIDX 0 329 #define CONFIG_HAS_ETH1 330 331 #define CONFIG_TSEC3 1 332 #define CONFIG_TSEC3_NAME "eTSEC3" 333 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 334 #define TSEC3_PHY_ADDR 3 335 #define TSEC3_PHYIDX 0 336 #define CONFIG_HAS_ETH2 337 338 /* 339 * USB 340 */ 341 #define CONFIG_USB_EHCI 342 #define CONFIG_USB_EHCI_FSL 343 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 344 #define CONFIG_DOS_PARTITION 345 346 /* 347 * Command configuration. 348 */ 349 #define CONFIG_CMD_DATE 350 #define CONFIG_CMD_DTT 351 #define CONFIG_CMD_EEPROM 352 #define CONFIG_CMD_JFFS2 353 #define CONFIG_CMD_NAND 354 #define CONFIG_CMD_PCA953X 355 #define CONFIG_CMD_PCA953X_INFO 356 #define CONFIG_CMD_PCI 357 #define CONFIG_CMD_PCI_ENUM 358 #define CONFIG_CMD_REGINFO 359 360 /* 361 * Miscellaneous configurable options 362 */ 363 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 364 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 365 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 366 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 367 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 368 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 369 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 370 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 371 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 372 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 373 #define CONFIG_PREBOOT /* enable preboot variable */ 374 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 375 376 /* 377 * For booting Linux, the board info and command line data 378 * have to be in the first 16 MB of memory, since this is 379 * the maximum mapped by the Linux kernel during initialization. 380 */ 381 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 382 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 383 384 /* 385 * Environment Configuration 386 */ 387 #define CONFIG_ENV_IS_IN_FLASH 1 388 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 389 #define CONFIG_ENV_SIZE 0x8000 390 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 391 392 /* 393 * Flash memory map: 394 * fff80000 - ffffffff Pri U-Boot (512 KB) 395 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 396 * fff00000 - fff3ffff Pri FDT (256KB) 397 * fef00000 - ffefffff Pri OS image (16MB) 398 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 399 * 400 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 401 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 402 * f7f00000 - f7f3ffff Sec FDT (256KB) 403 * f6f00000 - f7efffff Sec OS image (16MB) 404 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 405 */ 406 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 407 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 408 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 409 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 410 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 411 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 412 413 #define CONFIG_PROG_UBOOT1 \ 414 "$download_cmd $loadaddr $ubootfile; " \ 415 "if test $? -eq 0; then " \ 416 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 417 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 418 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 419 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 420 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 421 "if test $? -ne 0; then " \ 422 "echo PROGRAM FAILED; " \ 423 "else; " \ 424 "echo PROGRAM SUCCEEDED; " \ 425 "fi; " \ 426 "else; " \ 427 "echo DOWNLOAD FAILED; " \ 428 "fi;" 429 430 #define CONFIG_PROG_UBOOT2 \ 431 "$download_cmd $loadaddr $ubootfile; " \ 432 "if test $? -eq 0; then " \ 433 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 434 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 435 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 436 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 437 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 438 "if test $? -ne 0; then " \ 439 "echo PROGRAM FAILED; " \ 440 "else; " \ 441 "echo PROGRAM SUCCEEDED; " \ 442 "fi; " \ 443 "else; " \ 444 "echo DOWNLOAD FAILED; " \ 445 "fi;" 446 447 #define CONFIG_BOOT_OS_NET \ 448 "$download_cmd $osaddr $osfile; " \ 449 "if test $? -eq 0; then " \ 450 "if test -n $fdtaddr; then " \ 451 "$download_cmd $fdtaddr $fdtfile; " \ 452 "if test $? -eq 0; then " \ 453 "bootm $osaddr - $fdtaddr; " \ 454 "else; " \ 455 "echo FDT DOWNLOAD FAILED; " \ 456 "fi; " \ 457 "else; " \ 458 "bootm $osaddr; " \ 459 "fi; " \ 460 "else; " \ 461 "echo OS DOWNLOAD FAILED; " \ 462 "fi;" 463 464 #define CONFIG_PROG_OS1 \ 465 "$download_cmd $osaddr $osfile; " \ 466 "if test $? -eq 0; then " \ 467 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 468 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 469 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 470 "if test $? -ne 0; then " \ 471 "echo OS PROGRAM FAILED; " \ 472 "else; " \ 473 "echo OS PROGRAM SUCCEEDED; " \ 474 "fi; " \ 475 "else; " \ 476 "echo OS DOWNLOAD FAILED; " \ 477 "fi;" 478 479 #define CONFIG_PROG_OS2 \ 480 "$download_cmd $osaddr $osfile; " \ 481 "if test $? -eq 0; then " \ 482 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 483 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 484 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 485 "if test $? -ne 0; then " \ 486 "echo OS PROGRAM FAILED; " \ 487 "else; " \ 488 "echo OS PROGRAM SUCCEEDED; " \ 489 "fi; " \ 490 "else; " \ 491 "echo OS DOWNLOAD FAILED; " \ 492 "fi;" 493 494 #define CONFIG_PROG_FDT1 \ 495 "$download_cmd $fdtaddr $fdtfile; " \ 496 "if test $? -eq 0; then " \ 497 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 498 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 499 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 500 "if test $? -ne 0; then " \ 501 "echo FDT PROGRAM FAILED; " \ 502 "else; " \ 503 "echo FDT PROGRAM SUCCEEDED; " \ 504 "fi; " \ 505 "else; " \ 506 "echo FDT DOWNLOAD FAILED; " \ 507 "fi;" 508 509 #define CONFIG_PROG_FDT2 \ 510 "$download_cmd $fdtaddr $fdtfile; " \ 511 "if test $? -eq 0; then " \ 512 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 513 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 514 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 515 "if test $? -ne 0; then " \ 516 "echo FDT PROGRAM FAILED; " \ 517 "else; " \ 518 "echo FDT PROGRAM SUCCEEDED; " \ 519 "fi; " \ 520 "else; " \ 521 "echo FDT DOWNLOAD FAILED; " \ 522 "fi;" 523 524 #define CONFIG_EXTRA_ENV_SETTINGS \ 525 "autoload=yes\0" \ 526 "download_cmd=tftp\0" \ 527 "console_args=console=ttyS0,115200\0" \ 528 "root_args=root=/dev/nfs rw\0" \ 529 "misc_args=ip=on\0" \ 530 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 531 "bootfile=/home/user/file\0" \ 532 "osfile=/home/user/board.uImage\0" \ 533 "fdtfile=/home/user/board.dtb\0" \ 534 "ubootfile=/home/user/u-boot.bin\0" \ 535 "fdtaddr=0x1e00000\0" \ 536 "osaddr=0x1000000\0" \ 537 "loadaddr=0x1000000\0" \ 538 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 539 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 540 "prog_os1="CONFIG_PROG_OS1"\0" \ 541 "prog_os2="CONFIG_PROG_OS2"\0" \ 542 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 543 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 544 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 545 "bootcmd_flash1=run set_bootargs; " \ 546 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 547 "bootcmd_flash2=run set_bootargs; " \ 548 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 549 "bootcmd=run bootcmd_flash1\0" 550 #endif /* __CONFIG_H */ 551