1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite537x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_BOOKE		1	/* BOOKE */
18 #define CONFIG_E500		1	/* BOOKE e500 family */
19 #define CONFIG_MPC8572		1
20 #define CONFIG_XPEDITE5370	1
21 #define CONFIG_SYS_BOARD_NAME	"XPedite5370"
22 #define CONFIG_SYS_FORM_3U_VPX	1
23 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
24 #define CONFIG_SYS_GENERIC_BOARD
25 #define CONFIG_DISPLAY_BOARDINFO
26 
27 #ifndef CONFIG_SYS_TEXT_BASE
28 #define CONFIG_SYS_TEXT_BASE	0xfff80000
29 #endif
30 
31 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
32 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
33 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
34 #define CONFIG_PCIE1		1	/* PCIE controler 1 */
35 #define CONFIG_PCIE2		1	/* PCIE controler 2 */
36 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
37 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
38 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
39 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
40 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
41 #define CONFIG_FSL_ELBC		1
42 
43 /*
44  * Multicore config
45  */
46 #define CONFIG_MP
47 #define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
48 #define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
49 
50 /*
51  * DDR config
52  */
53 #define CONFIG_SYS_FSL_DDR2
54 #undef CONFIG_FSL_DDR_INTERACTIVE
55 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
56 #define CONFIG_DDR_SPD
57 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
58 #define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
59 #define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
60 #define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
61 #define CONFIG_NUM_DDR_CONTROLLERS	2
62 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
63 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
64 #define CONFIG_DDR_ECC
65 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
66 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
67 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
68 #define CONFIG_VERY_BIG_RAM
69 
70 #ifndef __ASSEMBLY__
71 extern unsigned long get_board_sys_clk(unsigned long dummy);
72 extern unsigned long get_board_ddr_clk(unsigned long dummy);
73 #endif
74 
75 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
76 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
77 
78 /*
79  * These can be toggled for performance analysis, otherwise use default.
80  */
81 #define CONFIG_L2_CACHE			/* toggle L2 cache */
82 #define CONFIG_BTB			/* toggle branch predition */
83 #define CONFIG_ENABLE_36BIT_PHYS	1
84 
85 #define CONFIG_SYS_CCSRBAR		0xef000000
86 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
87 
88 /*
89  * Diagnostics
90  */
91 #define CONFIG_SYS_ALT_MEMTEST
92 #define CONFIG_SYS_MEMTEST_START	0x10000000
93 #define CONFIG_SYS_MEMTEST_END		0x20000000
94 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
95 					 CONFIG_SYS_POST_I2C)
96 #define I2C_ADDR_LIST			{CONFIG_SYS_I2C_DS1621_ADDR,	\
97 					 CONFIG_SYS_I2C_DS4510_ADDR,	\
98 					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
99 					 CONFIG_SYS_I2C_LM90_ADDR,	\
100 					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
101 					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
102 					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
103 					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
104 					 CONFIG_SYS_I2C_PEX8518_ADDR,	\
105 					 CONFIG_SYS_I2C_RTC_ADDR}
106 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
107 #define I2C_ADDR_IGNORE_LIST		{0x50}
108 
109 /*
110  * Memory map
111  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
112  * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
113  * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
114  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
115  * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
116  * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
117  * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
118  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
119  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
120  * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
121  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
122  */
123 
124 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
125 
126 /*
127  * NAND flash configuration
128  */
129 #define CONFIG_SYS_NAND_BASE		0xef800000
130 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
131 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
132 					 CONFIG_SYS_NAND_BASE2}
133 #define CONFIG_SYS_MAX_NAND_DEVICE	2
134 #define CONFIG_NAND_FSL_ELBC
135 
136 /*
137  * NOR flash configuration
138  */
139 #define CONFIG_SYS_FLASH_BASE		0xf8000000
140 #define CONFIG_SYS_FLASH_BASE2		0xf0000000
141 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
142 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
143 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
144 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
145 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
146 #define CONFIG_FLASH_CFI_DRIVER
147 #define CONFIG_SYS_FLASH_CFI
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
149 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
150 						  {0xf7f40000, 0xc0000} }
151 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
152 
153 /*
154  * Chip select configuration
155  */
156 /* NOR Flash 0 on CS0 */
157 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
158 				 BR_PS_16		| \
159 				 BR_V)
160 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
161 				 OR_GPCM_CSNT		| \
162 				 OR_GPCM_XACS		| \
163 				 OR_GPCM_ACS_DIV2	| \
164 				 OR_GPCM_SCY_8		| \
165 				 OR_GPCM_TRLX		| \
166 				 OR_GPCM_EHTR		| \
167 				 OR_GPCM_EAD)
168 
169 /* NOR Flash 1 on CS1 */
170 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
171 				 BR_PS_16		| \
172 				 BR_V)
173 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
174 
175 /* NAND flash on CS2 */
176 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
177 				 (2<<BR_DECC_SHIFT)	| \
178 				 BR_PS_8		| \
179 				 BR_MS_FCM		| \
180 				 BR_V)
181 
182 /* NAND flash on CS2 */
183 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
184 				 OR_FCM_PGS	| \
185 				 OR_FCM_CSCT	| \
186 				 OR_FCM_CST	| \
187 				 OR_FCM_CHT	| \
188 				 OR_FCM_SCY_1	| \
189 				 OR_FCM_TRLX	| \
190 				 OR_FCM_EHTR)
191 
192 /* NAND flash on CS3 */
193 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
194 				 (2<<BR_DECC_SHIFT)	| \
195 				 BR_PS_8		| \
196 				 BR_MS_FCM		| \
197 				 BR_V)
198 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
199 
200 /*
201  * Use L1 as initial stack
202  */
203 #define CONFIG_SYS_INIT_RAM_LOCK	1
204 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
205 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
206 
207 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
208 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
209 
210 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
211 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
212 
213 /*
214  * Serial Port
215  */
216 #define CONFIG_CONS_INDEX		1
217 #define CONFIG_SYS_NS16550
218 #define CONFIG_SYS_NS16550_SERIAL
219 #define CONFIG_SYS_NS16550_REG_SIZE	1
220 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
221 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
222 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
223 #define CONFIG_SYS_BAUDRATE_TABLE	\
224 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
225 #define CONFIG_BAUDRATE			115200
226 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
227 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
228 
229 /*
230  * Use the HUSH parser
231  */
232 #define CONFIG_SYS_HUSH_PARSER
233 
234 /*
235  * Pass open firmware flat tree
236  */
237 #define CONFIG_OF_LIBFDT		1
238 #define CONFIG_OF_BOARD_SETUP		1
239 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
240 
241 /*
242  * I2C
243  */
244 #define CONFIG_SYS_I2C
245 #define CONFIG_SYS_I2C_FSL
246 #define CONFIG_SYS_FSL_I2C_SPEED	400000
247 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
248 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
249 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
250 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
251 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
252 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
253 
254 /* PEX8518 slave I2C interface */
255 #define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
256 
257 /* I2C DS1631 temperature sensor */
258 #define CONFIG_SYS_I2C_DS1621_ADDR	0x48
259 #define CONFIG_DTT_DS1621
260 #define CONFIG_DTT_SENSORS		{ 0 }
261 #define CONFIG_SYS_I2C_LM90_ADDR	0x4c
262 
263 /* I2C EEPROM - AT24C128B */
264 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
265 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
267 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
268 
269 /* I2C RTC */
270 #define CONFIG_RTC_M41T11		1
271 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
272 #define CONFIG_SYS_M41T11_BASE_YEAR	2000
273 
274 /* GPIO/EEPROM/SRAM */
275 #define CONFIG_DS4510
276 #define CONFIG_SYS_I2C_DS4510_ADDR	0x51
277 
278 /* GPIO */
279 #define CONFIG_PCA953X
280 #define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
281 #define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
282 #define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
283 #define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
284 #define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
285 
286 /*
287  * PU = pulled high, PD = pulled low
288  * I = input, O = output, IO = input/output
289  */
290 /* PCA9557 @ 0x18*/
291 #define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
292 #define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
293 #define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
294 #define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
295 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
296 #define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
297 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
298 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
299 
300 /* PCA9557 @ 0x1c*/
301 #define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
302 #define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
303 #define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
304 #define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
305 #define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
306 #define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
307 #define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
308 #define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
309 
310 /* PCA9557 @ 0x1e*/
311 #define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
312 #define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
313 #define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
314 #define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
315 #define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
316 #define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
317 #define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
318 
319 /* PCA9557 @ 0x1f */
320 #define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
321 #define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
322 #define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
323 #define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
324 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
325 
326 /*
327  * General PCI
328  * Memory space is mapped 1-1, but I/O space must start from 0.
329  */
330 /* PCIE1 - VPX P1 */
331 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
332 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
333 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
334 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
335 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
336 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
337 
338 /* PCIE2 - PEX8518 */
339 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
340 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
341 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
342 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
343 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
344 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
345 
346 /*
347  * Networking options
348  */
349 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
350 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
351 #define CONFIG_TSEC_TBI
352 #define CONFIG_MII		1	/* MII PHY management */
353 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
354 #define CONFIG_ETHPRIME		"eTSEC2"
355 
356 /*
357  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
358  * 1000mbps SGMII link
359  */
360 #define CONFIG_TSEC_TBICR_SETTINGS ( \
361 		TBICR_PHY_RESET \
362 		| TBICR_FULL_DUPLEX \
363 		| TBICR_SPEED1_SET \
364 		)
365 
366 #define CONFIG_TSEC1		1
367 #define CONFIG_TSEC1_NAME	"eTSEC1"
368 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
369 #define TSEC1_PHY_ADDR		1
370 #define TSEC1_PHYIDX		0
371 #define CONFIG_HAS_ETH0
372 
373 #define CONFIG_TSEC2		1
374 #define CONFIG_TSEC2_NAME	"eTSEC2"
375 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
376 #define TSEC2_PHY_ADDR		2
377 #define TSEC2_PHYIDX		0
378 #define CONFIG_HAS_ETH1
379 
380 /*
381  * Command configuration.
382  */
383 #define CONFIG_CMD_ASKENV
384 #define CONFIG_CMD_DATE
385 #define CONFIG_CMD_DHCP
386 #define CONFIG_CMD_DS4510
387 #define CONFIG_CMD_DS4510_INFO
388 #define CONFIG_CMD_DTT
389 #define CONFIG_CMD_EEPROM
390 #define CONFIG_CMD_I2C
391 #define CONFIG_CMD_JFFS2
392 #define CONFIG_CMD_MII
393 #define CONFIG_CMD_NAND
394 #define CONFIG_CMD_PCA953X
395 #define CONFIG_CMD_PCA953X_INFO
396 #define CONFIG_CMD_PCI
397 #define CONFIG_CMD_PCI_ENUM
398 #define CONFIG_CMD_PING
399 #define CONFIG_CMD_SNTP
400 #define CONFIG_CMD_REGINFO
401 
402 /*
403  * Miscellaneous configurable options
404  */
405 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
406 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
407 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
408 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
409 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
410 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
411 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
412 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
413 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
414 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
415 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
416 #define CONFIG_PREBOOT				/* enable preboot variable */
417 #define CONFIG_FIT		1
418 #define CONFIG_FIT_VERBOSE	1
419 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
420 
421 /*
422  * For booting Linux, the board info and command line data
423  * have to be in the first 16 MB of memory, since this is
424  * the maximum mapped by the Linux kernel during initialization.
425  */
426 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
427 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
428 
429 /*
430  * Environment Configuration
431  */
432 #define CONFIG_ENV_IS_IN_FLASH	1
433 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
434 #define CONFIG_ENV_SIZE		0x8000
435 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
436 
437 /*
438  * Flash memory map:
439  * fff80000 - ffffffff     Pri U-Boot (512 KB)
440  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
441  * fff00000 - fff3ffff     Pri FDT (256KB)
442  * fef00000 - ffefffff     Pri OS image (16MB)
443  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
444  *
445  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
446  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
447  * f7f00000 - f7f3ffff     Sec FDT (256KB)
448  * f6f00000 - f7efffff     Sec OS image (16MB)
449  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
450  */
451 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
452 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
453 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
454 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
455 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
456 #define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
457 
458 #define CONFIG_PROG_UBOOT1						\
459 	"$download_cmd $loadaddr $ubootfile; "				\
460 	"if test $? -eq 0; then "					\
461 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
462 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
463 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
464 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
465 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
466 		"if test $? -ne 0; then "				\
467 			"echo PROGRAM FAILED; "				\
468 		"else; "						\
469 			"echo PROGRAM SUCCEEDED; "			\
470 		"fi; "							\
471 	"else; "							\
472 		"echo DOWNLOAD FAILED; "				\
473 	"fi;"
474 
475 #define CONFIG_PROG_UBOOT2						\
476 	"$download_cmd $loadaddr $ubootfile; "				\
477 	"if test $? -eq 0; then "					\
478 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
479 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
480 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
481 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
482 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
483 		"if test $? -ne 0; then "				\
484 			"echo PROGRAM FAILED; "				\
485 		"else; "						\
486 			"echo PROGRAM SUCCEEDED; "			\
487 		"fi; "							\
488 	"else; "							\
489 		"echo DOWNLOAD FAILED; "				\
490 	"fi;"
491 
492 #define CONFIG_BOOT_OS_NET						\
493 	"$download_cmd $osaddr $osfile; "				\
494 	"if test $? -eq 0; then "					\
495 		"if test -n $fdtaddr; then "				\
496 			"$download_cmd $fdtaddr $fdtfile; "		\
497 			"if test $? -eq 0; then "			\
498 				"bootm $osaddr - $fdtaddr; "		\
499 			"else; "					\
500 				"echo FDT DOWNLOAD FAILED; "		\
501 			"fi; "						\
502 		"else; "						\
503 			"bootm $osaddr; "				\
504 		"fi; "							\
505 	"else; "							\
506 		"echo OS DOWNLOAD FAILED; "				\
507 	"fi;"
508 
509 #define CONFIG_PROG_OS1							\
510 	"$download_cmd $osaddr $osfile; "				\
511 	"if test $? -eq 0; then "					\
512 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
513 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
514 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
515 		"if test $? -ne 0; then "				\
516 			"echo OS PROGRAM FAILED; "			\
517 		"else; "						\
518 			"echo OS PROGRAM SUCCEEDED; "			\
519 		"fi; "							\
520 	"else; "							\
521 		"echo OS DOWNLOAD FAILED; "				\
522 	"fi;"
523 
524 #define CONFIG_PROG_OS2							\
525 	"$download_cmd $osaddr $osfile; "				\
526 	"if test $? -eq 0; then "					\
527 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
528 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
529 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
530 		"if test $? -ne 0; then "				\
531 			"echo OS PROGRAM FAILED; "			\
532 		"else; "						\
533 			"echo OS PROGRAM SUCCEEDED; "			\
534 		"fi; "							\
535 	"else; "							\
536 		"echo OS DOWNLOAD FAILED; "				\
537 	"fi;"
538 
539 #define CONFIG_PROG_FDT1						\
540 	"$download_cmd $fdtaddr $fdtfile; "				\
541 	"if test $? -eq 0; then "					\
542 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
543 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
544 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
545 		"if test $? -ne 0; then "				\
546 			"echo FDT PROGRAM FAILED; "			\
547 		"else; "						\
548 			"echo FDT PROGRAM SUCCEEDED; "			\
549 		"fi; "							\
550 	"else; "							\
551 		"echo FDT DOWNLOAD FAILED; "				\
552 	"fi;"
553 
554 #define CONFIG_PROG_FDT2						\
555 	"$download_cmd $fdtaddr $fdtfile; "				\
556 	"if test $? -eq 0; then "					\
557 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
558 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
559 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
560 		"if test $? -ne 0; then "				\
561 			"echo FDT PROGRAM FAILED; "			\
562 		"else; "						\
563 			"echo FDT PROGRAM SUCCEEDED; "			\
564 		"fi; "							\
565 	"else; "							\
566 		"echo FDT DOWNLOAD FAILED; "				\
567 	"fi;"
568 
569 #define	CONFIG_EXTRA_ENV_SETTINGS					\
570 	"autoload=yes\0"						\
571 	"download_cmd=tftp\0"						\
572 	"console_args=console=ttyS0,115200\0"				\
573 	"root_args=root=/dev/nfs rw\0"					\
574 	"misc_args=ip=on\0"						\
575 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
576 	"bootfile=/home/user/file\0"					\
577 	"osfile=/home/user/board.uImage\0"				\
578 	"fdtfile=/home/user/board.dtb\0"				\
579 	"ubootfile=/home/user/u-boot.bin\0"				\
580 	"fdtaddr=c00000\0"						\
581 	"osaddr=0x1000000\0"						\
582 	"loadaddr=0x1000000\0"						\
583 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
584 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
585 	"prog_os1="CONFIG_PROG_OS1"\0"					\
586 	"prog_os2="CONFIG_PROG_OS2"\0"					\
587 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
588 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
589 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
590 	"bootcmd_flash1=run set_bootargs; "				\
591 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
592 	"bootcmd_flash2=run set_bootargs; "				\
593 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
594 	"bootcmd=run bootcmd_flash1\0"
595 #endif	/* __CONFIG_H */
596