1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite537x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_SYS_BOARD_NAME	"XPedite5370"
18 #define CONFIG_SYS_FORM_3U_VPX	1
19 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
20 
21 #ifndef CONFIG_SYS_TEXT_BASE
22 #define CONFIG_SYS_TEXT_BASE	0xfff80000
23 #endif
24 
25 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
26 #define CONFIG_PCIE1		1	/* PCIE controller 1 */
27 #define CONFIG_PCIE2		1	/* PCIE controller 2 */
28 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
29 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
30 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
31 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
32 
33 /*
34  * Multicore config
35  */
36 #define CONFIG_MP
37 #define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
38 #define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
39 
40 /*
41  * DDR config
42  */
43 #undef CONFIG_FSL_DDR_INTERACTIVE
44 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
45 #define CONFIG_DDR_SPD
46 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
48 #define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
49 #define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
50 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
51 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
52 #define CONFIG_DDR_ECC
53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
54 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
55 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
56 #define CONFIG_VERY_BIG_RAM
57 
58 #ifndef __ASSEMBLY__
59 extern unsigned long get_board_sys_clk(unsigned long dummy);
60 extern unsigned long get_board_ddr_clk(unsigned long dummy);
61 #endif
62 
63 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
64 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
65 
66 /*
67  * These can be toggled for performance analysis, otherwise use default.
68  */
69 #define CONFIG_L2_CACHE			/* toggle L2 cache */
70 #define CONFIG_BTB			/* toggle branch predition */
71 #define CONFIG_ENABLE_36BIT_PHYS	1
72 
73 #define CONFIG_SYS_CCSRBAR		0xef000000
74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
75 
76 /*
77  * Diagnostics
78  */
79 #define CONFIG_SYS_ALT_MEMTEST
80 #define CONFIG_SYS_MEMTEST_START	0x10000000
81 #define CONFIG_SYS_MEMTEST_END		0x20000000
82 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
83 					 CONFIG_SYS_POST_I2C)
84 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
85 #define I2C_ADDR_IGNORE_LIST		{0x50}
86 
87 /*
88  * Memory map
89  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
90  * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
91  * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
92  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
93  * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
94  * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
95  * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
96  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
97  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
98  * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
99  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
100  */
101 
102 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
103 
104 /*
105  * NAND flash configuration
106  */
107 #define CONFIG_SYS_NAND_BASE		0xef800000
108 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
109 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
110 					 CONFIG_SYS_NAND_BASE2}
111 #define CONFIG_SYS_MAX_NAND_DEVICE	2
112 #define CONFIG_NAND_FSL_ELBC
113 
114 /*
115  * NOR flash configuration
116  */
117 #define CONFIG_SYS_FLASH_BASE		0xf8000000
118 #define CONFIG_SYS_FLASH_BASE2		0xf0000000
119 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
120 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
121 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
122 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
123 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
124 #define CONFIG_FLASH_CFI_DRIVER
125 #define CONFIG_SYS_FLASH_CFI
126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
127 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
128 						  {0xf7f40000, 0xc0000} }
129 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
130 
131 /*
132  * Chip select configuration
133  */
134 /* NOR Flash 0 on CS0 */
135 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
136 				 BR_PS_16		| \
137 				 BR_V)
138 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
139 				 OR_GPCM_CSNT		| \
140 				 OR_GPCM_XACS		| \
141 				 OR_GPCM_ACS_DIV2	| \
142 				 OR_GPCM_SCY_8		| \
143 				 OR_GPCM_TRLX		| \
144 				 OR_GPCM_EHTR		| \
145 				 OR_GPCM_EAD)
146 
147 /* NOR Flash 1 on CS1 */
148 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
149 				 BR_PS_16		| \
150 				 BR_V)
151 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
152 
153 /* NAND flash on CS2 */
154 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
155 				 (2<<BR_DECC_SHIFT)	| \
156 				 BR_PS_8		| \
157 				 BR_MS_FCM		| \
158 				 BR_V)
159 
160 /* NAND flash on CS2 */
161 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
162 				 OR_FCM_PGS	| \
163 				 OR_FCM_CSCT	| \
164 				 OR_FCM_CST	| \
165 				 OR_FCM_CHT	| \
166 				 OR_FCM_SCY_1	| \
167 				 OR_FCM_TRLX	| \
168 				 OR_FCM_EHTR)
169 
170 /* NAND flash on CS3 */
171 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
172 				 (2<<BR_DECC_SHIFT)	| \
173 				 BR_PS_8		| \
174 				 BR_MS_FCM		| \
175 				 BR_V)
176 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
177 
178 /*
179  * Use L1 as initial stack
180  */
181 #define CONFIG_SYS_INIT_RAM_LOCK	1
182 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
183 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
184 
185 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
186 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
187 
188 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
189 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
190 
191 /*
192  * Serial Port
193  */
194 #define CONFIG_CONS_INDEX		1
195 #define CONFIG_SYS_NS16550_SERIAL
196 #define CONFIG_SYS_NS16550_REG_SIZE	1
197 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
198 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
199 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
200 #define CONFIG_SYS_BAUDRATE_TABLE	\
201 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
202 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
203 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
204 
205 /*
206  * I2C
207  */
208 #define CONFIG_SYS_I2C
209 #define CONFIG_SYS_I2C_FSL
210 #define CONFIG_SYS_FSL_I2C_SPEED	400000
211 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
212 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
213 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
214 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
215 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
216 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
217 
218 /* PEX8518 slave I2C interface */
219 #define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
220 
221 /* I2C DS1631 temperature sensor */
222 #define CONFIG_SYS_I2C_LM90_ADDR	0x4c
223 
224 /* I2C EEPROM - AT24C128B */
225 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
226 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
227 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
229 
230 /* I2C RTC */
231 #define CONFIG_RTC_M41T11		1
232 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
233 #define CONFIG_SYS_M41T11_BASE_YEAR	2000
234 
235 /* GPIO */
236 #define CONFIG_PCA953X
237 #define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
238 #define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
239 #define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
240 #define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
241 #define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
242 
243 /*
244  * PU = pulled high, PD = pulled low
245  * I = input, O = output, IO = input/output
246  */
247 /* PCA9557 @ 0x18*/
248 #define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
249 #define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
250 #define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
251 #define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
252 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
253 #define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
254 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
255 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
256 
257 /* PCA9557 @ 0x1c*/
258 #define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
259 #define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
260 #define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
261 #define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
262 #define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
263 #define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
264 #define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
265 #define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
266 
267 /* PCA9557 @ 0x1e*/
268 #define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
269 #define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
270 #define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
271 #define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
272 #define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
273 #define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
274 #define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
275 
276 /* PCA9557 @ 0x1f */
277 #define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
278 #define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
279 #define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
280 #define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
281 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
282 
283 /*
284  * General PCI
285  * Memory space is mapped 1-1, but I/O space must start from 0.
286  */
287 /* PCIE1 - VPX P1 */
288 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
289 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
290 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
291 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
292 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
293 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
294 
295 /* PCIE2 - PEX8518 */
296 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
297 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
298 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
299 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
300 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
301 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
302 
303 /*
304  * Networking options
305  */
306 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
307 #define CONFIG_TSEC_TBI
308 #define CONFIG_MII		1	/* MII PHY management */
309 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
310 #define CONFIG_ETHPRIME		"eTSEC2"
311 
312 /*
313  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
314  * 1000mbps SGMII link
315  */
316 #define CONFIG_TSEC_TBICR_SETTINGS ( \
317 		TBICR_PHY_RESET \
318 		| TBICR_FULL_DUPLEX \
319 		| TBICR_SPEED1_SET \
320 		)
321 
322 #define CONFIG_TSEC1		1
323 #define CONFIG_TSEC1_NAME	"eTSEC1"
324 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
325 #define TSEC1_PHY_ADDR		1
326 #define TSEC1_PHYIDX		0
327 #define CONFIG_HAS_ETH0
328 
329 #define CONFIG_TSEC2		1
330 #define CONFIG_TSEC2_NAME	"eTSEC2"
331 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
332 #define TSEC2_PHY_ADDR		2
333 #define TSEC2_PHYIDX		0
334 #define CONFIG_HAS_ETH1
335 
336 /*
337  * Miscellaneous configurable options
338  */
339 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
340 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
341 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
342 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
343 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
344 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
345 #define CONFIG_PREBOOT				/* enable preboot variable */
346 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
347 
348 /*
349  * For booting Linux, the board info and command line data
350  * have to be in the first 16 MB of memory, since this is
351  * the maximum mapped by the Linux kernel during initialization.
352  */
353 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
354 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
355 
356 /*
357  * Environment Configuration
358  */
359 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
360 #define CONFIG_ENV_SIZE		0x8000
361 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
362 
363 /*
364  * Flash memory map:
365  * fff80000 - ffffffff     Pri U-Boot (512 KB)
366  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
367  * fff00000 - fff3ffff     Pri FDT (256KB)
368  * fef00000 - ffefffff     Pri OS image (16MB)
369  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
370  *
371  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
372  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
373  * f7f00000 - f7f3ffff     Sec FDT (256KB)
374  * f6f00000 - f7efffff     Sec OS image (16MB)
375  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
376  */
377 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
378 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
379 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
380 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
381 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
382 #define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
383 
384 #define CONFIG_PROG_UBOOT1						\
385 	"$download_cmd $loadaddr $ubootfile; "				\
386 	"if test $? -eq 0; then "					\
387 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
388 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
389 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
390 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
391 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
392 		"if test $? -ne 0; then "				\
393 			"echo PROGRAM FAILED; "				\
394 		"else; "						\
395 			"echo PROGRAM SUCCEEDED; "			\
396 		"fi; "							\
397 	"else; "							\
398 		"echo DOWNLOAD FAILED; "				\
399 	"fi;"
400 
401 #define CONFIG_PROG_UBOOT2						\
402 	"$download_cmd $loadaddr $ubootfile; "				\
403 	"if test $? -eq 0; then "					\
404 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
405 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
406 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
407 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
408 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
409 		"if test $? -ne 0; then "				\
410 			"echo PROGRAM FAILED; "				\
411 		"else; "						\
412 			"echo PROGRAM SUCCEEDED; "			\
413 		"fi; "							\
414 	"else; "							\
415 		"echo DOWNLOAD FAILED; "				\
416 	"fi;"
417 
418 #define CONFIG_BOOT_OS_NET						\
419 	"$download_cmd $osaddr $osfile; "				\
420 	"if test $? -eq 0; then "					\
421 		"if test -n $fdtaddr; then "				\
422 			"$download_cmd $fdtaddr $fdtfile; "		\
423 			"if test $? -eq 0; then "			\
424 				"bootm $osaddr - $fdtaddr; "		\
425 			"else; "					\
426 				"echo FDT DOWNLOAD FAILED; "		\
427 			"fi; "						\
428 		"else; "						\
429 			"bootm $osaddr; "				\
430 		"fi; "							\
431 	"else; "							\
432 		"echo OS DOWNLOAD FAILED; "				\
433 	"fi;"
434 
435 #define CONFIG_PROG_OS1							\
436 	"$download_cmd $osaddr $osfile; "				\
437 	"if test $? -eq 0; then "					\
438 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
439 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
440 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
441 		"if test $? -ne 0; then "				\
442 			"echo OS PROGRAM FAILED; "			\
443 		"else; "						\
444 			"echo OS PROGRAM SUCCEEDED; "			\
445 		"fi; "							\
446 	"else; "							\
447 		"echo OS DOWNLOAD FAILED; "				\
448 	"fi;"
449 
450 #define CONFIG_PROG_OS2							\
451 	"$download_cmd $osaddr $osfile; "				\
452 	"if test $? -eq 0; then "					\
453 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
454 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
455 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
456 		"if test $? -ne 0; then "				\
457 			"echo OS PROGRAM FAILED; "			\
458 		"else; "						\
459 			"echo OS PROGRAM SUCCEEDED; "			\
460 		"fi; "							\
461 	"else; "							\
462 		"echo OS DOWNLOAD FAILED; "				\
463 	"fi;"
464 
465 #define CONFIG_PROG_FDT1						\
466 	"$download_cmd $fdtaddr $fdtfile; "				\
467 	"if test $? -eq 0; then "					\
468 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
469 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
470 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
471 		"if test $? -ne 0; then "				\
472 			"echo FDT PROGRAM FAILED; "			\
473 		"else; "						\
474 			"echo FDT PROGRAM SUCCEEDED; "			\
475 		"fi; "							\
476 	"else; "							\
477 		"echo FDT DOWNLOAD FAILED; "				\
478 	"fi;"
479 
480 #define CONFIG_PROG_FDT2						\
481 	"$download_cmd $fdtaddr $fdtfile; "				\
482 	"if test $? -eq 0; then "					\
483 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
484 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
485 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
486 		"if test $? -ne 0; then "				\
487 			"echo FDT PROGRAM FAILED; "			\
488 		"else; "						\
489 			"echo FDT PROGRAM SUCCEEDED; "			\
490 		"fi; "							\
491 	"else; "							\
492 		"echo FDT DOWNLOAD FAILED; "				\
493 	"fi;"
494 
495 #define	CONFIG_EXTRA_ENV_SETTINGS					\
496 	"autoload=yes\0"						\
497 	"download_cmd=tftp\0"						\
498 	"console_args=console=ttyS0,115200\0"				\
499 	"root_args=root=/dev/nfs rw\0"					\
500 	"misc_args=ip=on\0"						\
501 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
502 	"bootfile=/home/user/file\0"					\
503 	"osfile=/home/user/board.uImage\0"				\
504 	"fdtfile=/home/user/board.dtb\0"				\
505 	"ubootfile=/home/user/u-boot.bin\0"				\
506 	"fdtaddr=0x1e00000\0"						\
507 	"osaddr=0x1000000\0"						\
508 	"loadaddr=0x1000000\0"						\
509 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
510 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
511 	"prog_os1="CONFIG_PROG_OS1"\0"					\
512 	"prog_os2="CONFIG_PROG_OS2"\0"					\
513 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
514 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
515 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
516 	"bootcmd_flash1=run set_bootargs; "				\
517 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
518 	"bootcmd_flash2=run set_bootargs; "				\
519 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
520 	"bootcmd=run bootcmd_flash1\0"
521 #endif	/* __CONFIG_H */
522