1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite537x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_MPC8572 1 20 #define CONFIG_XPEDITE5370 1 21 #define CONFIG_SYS_BOARD_NAME "XPedite5370" 22 #define CONFIG_SYS_FORM_3U_VPX 1 23 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 24 #define CONFIG_DISPLAY_BOARDINFO 25 26 #ifndef CONFIG_SYS_TEXT_BASE 27 #define CONFIG_SYS_TEXT_BASE 0xfff80000 28 #endif 29 30 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 31 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ 32 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 33 #define CONFIG_PCIE1 1 /* PCIE controler 1 */ 34 #define CONFIG_PCIE2 1 /* PCIE controler 2 */ 35 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 36 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 37 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 38 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 39 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 40 #define CONFIG_FSL_ELBC 1 41 42 /* 43 * Multicore config 44 */ 45 #define CONFIG_MP 46 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 47 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 48 49 /* 50 * DDR config 51 */ 52 #define CONFIG_SYS_FSL_DDR2 53 #undef CONFIG_FSL_DDR_INTERACTIVE 54 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 55 #define CONFIG_DDR_SPD 56 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 57 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 58 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 59 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 60 #define CONFIG_NUM_DDR_CONTROLLERS 2 61 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 62 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 63 #define CONFIG_DDR_ECC 64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 65 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 67 #define CONFIG_VERY_BIG_RAM 68 69 #ifndef __ASSEMBLY__ 70 extern unsigned long get_board_sys_clk(unsigned long dummy); 71 extern unsigned long get_board_ddr_clk(unsigned long dummy); 72 #endif 73 74 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 75 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 76 77 /* 78 * These can be toggled for performance analysis, otherwise use default. 79 */ 80 #define CONFIG_L2_CACHE /* toggle L2 cache */ 81 #define CONFIG_BTB /* toggle branch predition */ 82 #define CONFIG_ENABLE_36BIT_PHYS 1 83 84 #define CONFIG_SYS_CCSRBAR 0xef000000 85 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 86 87 /* 88 * Diagnostics 89 */ 90 #define CONFIG_SYS_ALT_MEMTEST 91 #define CONFIG_SYS_MEMTEST_START 0x10000000 92 #define CONFIG_SYS_MEMTEST_END 0x20000000 93 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 94 CONFIG_SYS_POST_I2C) 95 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \ 96 CONFIG_SYS_I2C_DS4510_ADDR, \ 97 CONFIG_SYS_I2C_EEPROM_ADDR, \ 98 CONFIG_SYS_I2C_LM90_ADDR, \ 99 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 100 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 101 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 102 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 103 CONFIG_SYS_I2C_PEX8518_ADDR, \ 104 CONFIG_SYS_I2C_RTC_ADDR} 105 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ 106 #define I2C_ADDR_IGNORE_LIST {0x50} 107 108 /* 109 * Memory map 110 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 111 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 112 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 113 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 114 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 115 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 116 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 117 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 118 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 119 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 120 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 121 */ 122 123 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 124 125 /* 126 * NAND flash configuration 127 */ 128 #define CONFIG_SYS_NAND_BASE 0xef800000 129 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 130 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 131 CONFIG_SYS_NAND_BASE2} 132 #define CONFIG_SYS_MAX_NAND_DEVICE 2 133 #define CONFIG_NAND_FSL_ELBC 134 135 /* 136 * NOR flash configuration 137 */ 138 #define CONFIG_SYS_FLASH_BASE 0xf8000000 139 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 140 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 141 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 142 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 143 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 144 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 145 #define CONFIG_FLASH_CFI_DRIVER 146 #define CONFIG_SYS_FLASH_CFI 147 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 148 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 149 {0xf7f40000, 0xc0000} } 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 151 152 /* 153 * Chip select configuration 154 */ 155 /* NOR Flash 0 on CS0 */ 156 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 157 BR_PS_16 | \ 158 BR_V) 159 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 160 OR_GPCM_CSNT | \ 161 OR_GPCM_XACS | \ 162 OR_GPCM_ACS_DIV2 | \ 163 OR_GPCM_SCY_8 | \ 164 OR_GPCM_TRLX | \ 165 OR_GPCM_EHTR | \ 166 OR_GPCM_EAD) 167 168 /* NOR Flash 1 on CS1 */ 169 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 170 BR_PS_16 | \ 171 BR_V) 172 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 173 174 /* NAND flash on CS2 */ 175 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 176 (2<<BR_DECC_SHIFT) | \ 177 BR_PS_8 | \ 178 BR_MS_FCM | \ 179 BR_V) 180 181 /* NAND flash on CS2 */ 182 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 183 OR_FCM_PGS | \ 184 OR_FCM_CSCT | \ 185 OR_FCM_CST | \ 186 OR_FCM_CHT | \ 187 OR_FCM_SCY_1 | \ 188 OR_FCM_TRLX | \ 189 OR_FCM_EHTR) 190 191 /* NAND flash on CS3 */ 192 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 193 (2<<BR_DECC_SHIFT) | \ 194 BR_PS_8 | \ 195 BR_MS_FCM | \ 196 BR_V) 197 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 198 199 /* 200 * Use L1 as initial stack 201 */ 202 #define CONFIG_SYS_INIT_RAM_LOCK 1 203 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 204 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 205 206 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 207 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 208 209 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 210 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 211 212 /* 213 * Serial Port 214 */ 215 #define CONFIG_CONS_INDEX 1 216 #define CONFIG_SYS_NS16550_SERIAL 217 #define CONFIG_SYS_NS16550_REG_SIZE 1 218 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 219 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 220 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 221 #define CONFIG_SYS_BAUDRATE_TABLE \ 222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 223 #define CONFIG_BAUDRATE 115200 224 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 225 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 226 227 /* 228 * Use the HUSH parser 229 */ 230 #define CONFIG_SYS_HUSH_PARSER 231 232 /* 233 * I2C 234 */ 235 #define CONFIG_SYS_I2C 236 #define CONFIG_SYS_I2C_FSL 237 #define CONFIG_SYS_FSL_I2C_SPEED 400000 238 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 239 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 240 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 241 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 242 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 243 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 244 245 /* PEX8518 slave I2C interface */ 246 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 247 248 /* I2C DS1631 temperature sensor */ 249 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 250 #define CONFIG_DTT_DS1621 251 #define CONFIG_DTT_SENSORS { 0 } 252 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 253 254 /* I2C EEPROM - AT24C128B */ 255 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 256 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 259 260 /* I2C RTC */ 261 #define CONFIG_RTC_M41T11 1 262 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 263 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 264 265 /* GPIO/EEPROM/SRAM */ 266 #define CONFIG_DS4510 267 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 268 269 /* GPIO */ 270 #define CONFIG_PCA953X 271 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 272 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 273 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 274 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 275 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 276 277 /* 278 * PU = pulled high, PD = pulled low 279 * I = input, O = output, IO = input/output 280 */ 281 /* PCA9557 @ 0x18*/ 282 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 283 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 284 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 285 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 286 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 287 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 288 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ 289 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ 290 291 /* PCA9557 @ 0x1c*/ 292 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 293 #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ 294 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 295 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 296 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 297 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 298 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 299 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 300 301 /* PCA9557 @ 0x1e*/ 302 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 303 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 304 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 305 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 306 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 307 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ 308 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ 309 310 /* PCA9557 @ 0x1f */ 311 #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ 312 #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ 313 #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ 314 #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ 315 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ 316 317 /* 318 * General PCI 319 * Memory space is mapped 1-1, but I/O space must start from 0. 320 */ 321 /* PCIE1 - VPX P1 */ 322 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 323 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 324 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 325 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 326 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 327 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 328 329 /* PCIE2 - PEX8518 */ 330 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 331 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 332 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 333 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 334 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 335 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 336 337 /* 338 * Networking options 339 */ 340 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 341 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 342 #define CONFIG_TSEC_TBI 343 #define CONFIG_MII 1 /* MII PHY management */ 344 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 345 #define CONFIG_ETHPRIME "eTSEC2" 346 347 /* 348 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 349 * 1000mbps SGMII link 350 */ 351 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 352 TBICR_PHY_RESET \ 353 | TBICR_FULL_DUPLEX \ 354 | TBICR_SPEED1_SET \ 355 ) 356 357 #define CONFIG_TSEC1 1 358 #define CONFIG_TSEC1_NAME "eTSEC1" 359 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 360 #define TSEC1_PHY_ADDR 1 361 #define TSEC1_PHYIDX 0 362 #define CONFIG_HAS_ETH0 363 364 #define CONFIG_TSEC2 1 365 #define CONFIG_TSEC2_NAME "eTSEC2" 366 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 367 #define TSEC2_PHY_ADDR 2 368 #define TSEC2_PHYIDX 0 369 #define CONFIG_HAS_ETH1 370 371 /* 372 * Command configuration. 373 */ 374 #define CONFIG_CMD_ASKENV 375 #define CONFIG_CMD_DATE 376 #define CONFIG_CMD_DHCP 377 #define CONFIG_CMD_DS4510 378 #define CONFIG_CMD_DS4510_INFO 379 #define CONFIG_CMD_DTT 380 #define CONFIG_CMD_EEPROM 381 #define CONFIG_CMD_I2C 382 #define CONFIG_CMD_JFFS2 383 #define CONFIG_CMD_MII 384 #define CONFIG_CMD_NAND 385 #define CONFIG_CMD_PCA953X 386 #define CONFIG_CMD_PCA953X_INFO 387 #define CONFIG_CMD_PCI 388 #define CONFIG_CMD_PCI_ENUM 389 #define CONFIG_CMD_PING 390 #define CONFIG_CMD_SNTP 391 #define CONFIG_CMD_REGINFO 392 393 /* 394 * Miscellaneous configurable options 395 */ 396 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 397 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 398 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 399 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 400 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 401 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 402 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 403 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 404 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 405 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ 406 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 407 #define CONFIG_PREBOOT /* enable preboot variable */ 408 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 409 410 /* 411 * For booting Linux, the board info and command line data 412 * have to be in the first 16 MB of memory, since this is 413 * the maximum mapped by the Linux kernel during initialization. 414 */ 415 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 416 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 417 418 /* 419 * Environment Configuration 420 */ 421 #define CONFIG_ENV_IS_IN_FLASH 1 422 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 423 #define CONFIG_ENV_SIZE 0x8000 424 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 425 426 /* 427 * Flash memory map: 428 * fff80000 - ffffffff Pri U-Boot (512 KB) 429 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 430 * fff00000 - fff3ffff Pri FDT (256KB) 431 * fef00000 - ffefffff Pri OS image (16MB) 432 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 433 * 434 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 435 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 436 * f7f00000 - f7f3ffff Sec FDT (256KB) 437 * f6f00000 - f7efffff Sec OS image (16MB) 438 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 439 */ 440 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 441 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 442 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 443 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 444 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 445 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 446 447 #define CONFIG_PROG_UBOOT1 \ 448 "$download_cmd $loadaddr $ubootfile; " \ 449 "if test $? -eq 0; then " \ 450 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 451 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 452 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 453 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 454 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 455 "if test $? -ne 0; then " \ 456 "echo PROGRAM FAILED; " \ 457 "else; " \ 458 "echo PROGRAM SUCCEEDED; " \ 459 "fi; " \ 460 "else; " \ 461 "echo DOWNLOAD FAILED; " \ 462 "fi;" 463 464 #define CONFIG_PROG_UBOOT2 \ 465 "$download_cmd $loadaddr $ubootfile; " \ 466 "if test $? -eq 0; then " \ 467 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 468 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 469 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 470 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 471 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 472 "if test $? -ne 0; then " \ 473 "echo PROGRAM FAILED; " \ 474 "else; " \ 475 "echo PROGRAM SUCCEEDED; " \ 476 "fi; " \ 477 "else; " \ 478 "echo DOWNLOAD FAILED; " \ 479 "fi;" 480 481 #define CONFIG_BOOT_OS_NET \ 482 "$download_cmd $osaddr $osfile; " \ 483 "if test $? -eq 0; then " \ 484 "if test -n $fdtaddr; then " \ 485 "$download_cmd $fdtaddr $fdtfile; " \ 486 "if test $? -eq 0; then " \ 487 "bootm $osaddr - $fdtaddr; " \ 488 "else; " \ 489 "echo FDT DOWNLOAD FAILED; " \ 490 "fi; " \ 491 "else; " \ 492 "bootm $osaddr; " \ 493 "fi; " \ 494 "else; " \ 495 "echo OS DOWNLOAD FAILED; " \ 496 "fi;" 497 498 #define CONFIG_PROG_OS1 \ 499 "$download_cmd $osaddr $osfile; " \ 500 "if test $? -eq 0; then " \ 501 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 502 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 503 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 504 "if test $? -ne 0; then " \ 505 "echo OS PROGRAM FAILED; " \ 506 "else; " \ 507 "echo OS PROGRAM SUCCEEDED; " \ 508 "fi; " \ 509 "else; " \ 510 "echo OS DOWNLOAD FAILED; " \ 511 "fi;" 512 513 #define CONFIG_PROG_OS2 \ 514 "$download_cmd $osaddr $osfile; " \ 515 "if test $? -eq 0; then " \ 516 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 517 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 518 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 519 "if test $? -ne 0; then " \ 520 "echo OS PROGRAM FAILED; " \ 521 "else; " \ 522 "echo OS PROGRAM SUCCEEDED; " \ 523 "fi; " \ 524 "else; " \ 525 "echo OS DOWNLOAD FAILED; " \ 526 "fi;" 527 528 #define CONFIG_PROG_FDT1 \ 529 "$download_cmd $fdtaddr $fdtfile; " \ 530 "if test $? -eq 0; then " \ 531 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 532 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 533 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 534 "if test $? -ne 0; then " \ 535 "echo FDT PROGRAM FAILED; " \ 536 "else; " \ 537 "echo FDT PROGRAM SUCCEEDED; " \ 538 "fi; " \ 539 "else; " \ 540 "echo FDT DOWNLOAD FAILED; " \ 541 "fi;" 542 543 #define CONFIG_PROG_FDT2 \ 544 "$download_cmd $fdtaddr $fdtfile; " \ 545 "if test $? -eq 0; then " \ 546 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 547 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 548 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 549 "if test $? -ne 0; then " \ 550 "echo FDT PROGRAM FAILED; " \ 551 "else; " \ 552 "echo FDT PROGRAM SUCCEEDED; " \ 553 "fi; " \ 554 "else; " \ 555 "echo FDT DOWNLOAD FAILED; " \ 556 "fi;" 557 558 #define CONFIG_EXTRA_ENV_SETTINGS \ 559 "autoload=yes\0" \ 560 "download_cmd=tftp\0" \ 561 "console_args=console=ttyS0,115200\0" \ 562 "root_args=root=/dev/nfs rw\0" \ 563 "misc_args=ip=on\0" \ 564 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 565 "bootfile=/home/user/file\0" \ 566 "osfile=/home/user/board.uImage\0" \ 567 "fdtfile=/home/user/board.dtb\0" \ 568 "ubootfile=/home/user/u-boot.bin\0" \ 569 "fdtaddr=c00000\0" \ 570 "osaddr=0x1000000\0" \ 571 "loadaddr=0x1000000\0" \ 572 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 573 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 574 "prog_os1="CONFIG_PROG_OS1"\0" \ 575 "prog_os2="CONFIG_PROG_OS2"\0" \ 576 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 577 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 578 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 579 "bootcmd_flash1=run set_bootargs; " \ 580 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 581 "bootcmd_flash2=run set_bootargs; " \ 582 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 583 "bootcmd=run bootcmd_flash1\0" 584 #endif /* __CONFIG_H */ 585