1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite537x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_SYS_BOARD_NAME "XPedite5370" 18 #define CONFIG_SYS_FORM_3U_VPX 1 19 20 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 21 #define CONFIG_PCIE1 1 /* PCIE controller 1 */ 22 #define CONFIG_PCIE2 1 /* PCIE controller 2 */ 23 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 24 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 26 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 27 28 /* 29 * Multicore config 30 */ 31 #define CONFIG_MP 32 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 33 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 34 35 /* 36 * DDR config 37 */ 38 #undef CONFIG_FSL_DDR_INTERACTIVE 39 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 40 #define CONFIG_DDR_SPD 41 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 42 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 43 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 44 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 45 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 46 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 47 #define CONFIG_DDR_ECC 48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 49 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 50 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 51 #define CONFIG_VERY_BIG_RAM 52 53 #ifndef __ASSEMBLY__ 54 extern unsigned long get_board_sys_clk(unsigned long dummy); 55 extern unsigned long get_board_ddr_clk(unsigned long dummy); 56 #endif 57 58 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 59 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_L2_CACHE /* toggle L2 cache */ 65 #define CONFIG_BTB /* toggle branch predition */ 66 #define CONFIG_ENABLE_36BIT_PHYS 1 67 68 #define CONFIG_SYS_CCSRBAR 0xef000000 69 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 70 71 /* 72 * Diagnostics 73 */ 74 #define CONFIG_SYS_MEMTEST_START 0x10000000 75 #define CONFIG_SYS_MEMTEST_END 0x20000000 76 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 77 CONFIG_SYS_POST_I2C) 78 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ 79 #define I2C_ADDR_IGNORE_LIST {0x50} 80 81 /* 82 * Memory map 83 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 84 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 85 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 86 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 87 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 88 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 89 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 90 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 91 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 92 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 93 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 94 */ 95 96 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 97 98 /* 99 * NAND flash configuration 100 */ 101 #define CONFIG_SYS_NAND_BASE 0xef800000 102 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 103 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 104 CONFIG_SYS_NAND_BASE2} 105 #define CONFIG_SYS_MAX_NAND_DEVICE 2 106 #define CONFIG_NAND_FSL_ELBC 107 108 /* 109 * NOR flash configuration 110 */ 111 #define CONFIG_SYS_FLASH_BASE 0xf8000000 112 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 113 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 114 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 115 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 116 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 117 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 118 #define CONFIG_FLASH_CFI_DRIVER 119 #define CONFIG_SYS_FLASH_CFI 120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 121 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 122 {0xf7f40000, 0xc0000} } 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 124 125 /* 126 * Chip select configuration 127 */ 128 /* NOR Flash 0 on CS0 */ 129 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 130 BR_PS_16 | \ 131 BR_V) 132 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 133 OR_GPCM_CSNT | \ 134 OR_GPCM_XACS | \ 135 OR_GPCM_ACS_DIV2 | \ 136 OR_GPCM_SCY_8 | \ 137 OR_GPCM_TRLX | \ 138 OR_GPCM_EHTR | \ 139 OR_GPCM_EAD) 140 141 /* NOR Flash 1 on CS1 */ 142 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 143 BR_PS_16 | \ 144 BR_V) 145 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 146 147 /* NAND flash on CS2 */ 148 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 149 (2<<BR_DECC_SHIFT) | \ 150 BR_PS_8 | \ 151 BR_MS_FCM | \ 152 BR_V) 153 154 /* NAND flash on CS2 */ 155 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 156 OR_FCM_PGS | \ 157 OR_FCM_CSCT | \ 158 OR_FCM_CST | \ 159 OR_FCM_CHT | \ 160 OR_FCM_SCY_1 | \ 161 OR_FCM_TRLX | \ 162 OR_FCM_EHTR) 163 164 /* NAND flash on CS3 */ 165 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 166 (2<<BR_DECC_SHIFT) | \ 167 BR_PS_8 | \ 168 BR_MS_FCM | \ 169 BR_V) 170 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 171 172 /* 173 * Use L1 as initial stack 174 */ 175 #define CONFIG_SYS_INIT_RAM_LOCK 1 176 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 177 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 178 179 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 181 182 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 183 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 184 185 /* 186 * Serial Port 187 */ 188 #define CONFIG_SYS_NS16550_SERIAL 189 #define CONFIG_SYS_NS16550_REG_SIZE 1 190 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 191 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 192 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 193 #define CONFIG_SYS_BAUDRATE_TABLE \ 194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 195 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 196 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 197 198 /* 199 * I2C 200 */ 201 #define CONFIG_SYS_I2C 202 #define CONFIG_SYS_I2C_FSL 203 #define CONFIG_SYS_FSL_I2C_SPEED 400000 204 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 205 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 206 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 207 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 208 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 209 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 210 211 /* PEX8518 slave I2C interface */ 212 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 213 214 /* I2C DS1631 temperature sensor */ 215 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 216 217 /* I2C EEPROM - AT24C128B */ 218 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 219 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 222 223 /* I2C RTC */ 224 #define CONFIG_RTC_M41T11 1 225 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 226 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 227 228 /* GPIO */ 229 #define CONFIG_PCA953X 230 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 231 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 232 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 233 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 234 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 235 236 /* 237 * PU = pulled high, PD = pulled low 238 * I = input, O = output, IO = input/output 239 */ 240 /* PCA9557 @ 0x18*/ 241 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 242 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 243 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 244 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 245 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 246 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 247 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ 248 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ 249 250 /* PCA9557 @ 0x1c*/ 251 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 252 #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ 253 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 254 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 255 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 256 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 257 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 258 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 259 260 /* PCA9557 @ 0x1e*/ 261 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 262 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 263 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 264 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 265 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 266 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ 267 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ 268 269 /* PCA9557 @ 0x1f */ 270 #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ 271 #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ 272 #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ 273 #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ 274 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ 275 276 /* 277 * General PCI 278 * Memory space is mapped 1-1, but I/O space must start from 0. 279 */ 280 /* PCIE1 - VPX P1 */ 281 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 282 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 283 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 284 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 285 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 286 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 287 288 /* PCIE2 - PEX8518 */ 289 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 290 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 291 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 292 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 293 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 294 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 295 296 /* 297 * Networking options 298 */ 299 #define CONFIG_TSEC_TBI 300 #define CONFIG_MII 1 /* MII PHY management */ 301 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 302 #define CONFIG_ETHPRIME "eTSEC2" 303 304 /* 305 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 306 * 1000mbps SGMII link 307 */ 308 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 309 TBICR_PHY_RESET \ 310 | TBICR_FULL_DUPLEX \ 311 | TBICR_SPEED1_SET \ 312 ) 313 314 #define CONFIG_TSEC1 1 315 #define CONFIG_TSEC1_NAME "eTSEC1" 316 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 317 #define TSEC1_PHY_ADDR 1 318 #define TSEC1_PHYIDX 0 319 #define CONFIG_HAS_ETH0 320 321 #define CONFIG_TSEC2 1 322 #define CONFIG_TSEC2_NAME "eTSEC2" 323 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 324 #define TSEC2_PHY_ADDR 2 325 #define TSEC2_PHYIDX 0 326 #define CONFIG_HAS_ETH1 327 328 /* 329 * Miscellaneous configurable options 330 */ 331 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 332 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 333 #define CONFIG_PREBOOT /* enable preboot variable */ 334 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 335 336 /* 337 * For booting Linux, the board info and command line data 338 * have to be in the first 16 MB of memory, since this is 339 * the maximum mapped by the Linux kernel during initialization. 340 */ 341 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 342 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 343 344 /* 345 * Environment Configuration 346 */ 347 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 348 #define CONFIG_ENV_SIZE 0x8000 349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 350 351 /* 352 * Flash memory map: 353 * fff80000 - ffffffff Pri U-Boot (512 KB) 354 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 355 * fff00000 - fff3ffff Pri FDT (256KB) 356 * fef00000 - ffefffff Pri OS image (16MB) 357 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 358 * 359 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 360 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 361 * f7f00000 - f7f3ffff Sec FDT (256KB) 362 * f6f00000 - f7efffff Sec OS image (16MB) 363 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 364 */ 365 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 366 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 367 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 368 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 369 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 370 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 371 372 #define CONFIG_PROG_UBOOT1 \ 373 "$download_cmd $loadaddr $ubootfile; " \ 374 "if test $? -eq 0; then " \ 375 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 376 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 377 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 378 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 379 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 380 "if test $? -ne 0; then " \ 381 "echo PROGRAM FAILED; " \ 382 "else; " \ 383 "echo PROGRAM SUCCEEDED; " \ 384 "fi; " \ 385 "else; " \ 386 "echo DOWNLOAD FAILED; " \ 387 "fi;" 388 389 #define CONFIG_PROG_UBOOT2 \ 390 "$download_cmd $loadaddr $ubootfile; " \ 391 "if test $? -eq 0; then " \ 392 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 393 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 394 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 395 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 396 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 397 "if test $? -ne 0; then " \ 398 "echo PROGRAM FAILED; " \ 399 "else; " \ 400 "echo PROGRAM SUCCEEDED; " \ 401 "fi; " \ 402 "else; " \ 403 "echo DOWNLOAD FAILED; " \ 404 "fi;" 405 406 #define CONFIG_BOOT_OS_NET \ 407 "$download_cmd $osaddr $osfile; " \ 408 "if test $? -eq 0; then " \ 409 "if test -n $fdtaddr; then " \ 410 "$download_cmd $fdtaddr $fdtfile; " \ 411 "if test $? -eq 0; then " \ 412 "bootm $osaddr - $fdtaddr; " \ 413 "else; " \ 414 "echo FDT DOWNLOAD FAILED; " \ 415 "fi; " \ 416 "else; " \ 417 "bootm $osaddr; " \ 418 "fi; " \ 419 "else; " \ 420 "echo OS DOWNLOAD FAILED; " \ 421 "fi;" 422 423 #define CONFIG_PROG_OS1 \ 424 "$download_cmd $osaddr $osfile; " \ 425 "if test $? -eq 0; then " \ 426 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 427 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 428 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 429 "if test $? -ne 0; then " \ 430 "echo OS PROGRAM FAILED; " \ 431 "else; " \ 432 "echo OS PROGRAM SUCCEEDED; " \ 433 "fi; " \ 434 "else; " \ 435 "echo OS DOWNLOAD FAILED; " \ 436 "fi;" 437 438 #define CONFIG_PROG_OS2 \ 439 "$download_cmd $osaddr $osfile; " \ 440 "if test $? -eq 0; then " \ 441 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 442 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 443 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 444 "if test $? -ne 0; then " \ 445 "echo OS PROGRAM FAILED; " \ 446 "else; " \ 447 "echo OS PROGRAM SUCCEEDED; " \ 448 "fi; " \ 449 "else; " \ 450 "echo OS DOWNLOAD FAILED; " \ 451 "fi;" 452 453 #define CONFIG_PROG_FDT1 \ 454 "$download_cmd $fdtaddr $fdtfile; " \ 455 "if test $? -eq 0; then " \ 456 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 457 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 458 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 459 "if test $? -ne 0; then " \ 460 "echo FDT PROGRAM FAILED; " \ 461 "else; " \ 462 "echo FDT PROGRAM SUCCEEDED; " \ 463 "fi; " \ 464 "else; " \ 465 "echo FDT DOWNLOAD FAILED; " \ 466 "fi;" 467 468 #define CONFIG_PROG_FDT2 \ 469 "$download_cmd $fdtaddr $fdtfile; " \ 470 "if test $? -eq 0; then " \ 471 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 472 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 473 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 474 "if test $? -ne 0; then " \ 475 "echo FDT PROGRAM FAILED; " \ 476 "else; " \ 477 "echo FDT PROGRAM SUCCEEDED; " \ 478 "fi; " \ 479 "else; " \ 480 "echo FDT DOWNLOAD FAILED; " \ 481 "fi;" 482 483 #define CONFIG_EXTRA_ENV_SETTINGS \ 484 "autoload=yes\0" \ 485 "download_cmd=tftp\0" \ 486 "console_args=console=ttyS0,115200\0" \ 487 "root_args=root=/dev/nfs rw\0" \ 488 "misc_args=ip=on\0" \ 489 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 490 "bootfile=/home/user/file\0" \ 491 "osfile=/home/user/board.uImage\0" \ 492 "fdtfile=/home/user/board.dtb\0" \ 493 "ubootfile=/home/user/u-boot.bin\0" \ 494 "fdtaddr=0x1e00000\0" \ 495 "osaddr=0x1000000\0" \ 496 "loadaddr=0x1000000\0" \ 497 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 498 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 499 "prog_os1="CONFIG_PROG_OS1"\0" \ 500 "prog_os2="CONFIG_PROG_OS2"\0" \ 501 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 502 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 503 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 504 "bootcmd_flash1=run set_bootargs; " \ 505 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 506 "bootcmd_flash2=run set_bootargs; " \ 507 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 508 "bootcmd=run bootcmd_flash1\0" 509 #endif /* __CONFIG_H */ 510