1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite537x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_SYS_BOARD_NAME "XPedite5370" 18 #define CONFIG_SYS_FORM_3U_VPX 1 19 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 20 21 #ifndef CONFIG_SYS_TEXT_BASE 22 #define CONFIG_SYS_TEXT_BASE 0xfff80000 23 #endif 24 25 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 26 #define CONFIG_PCIE1 1 /* PCIE controller 1 */ 27 #define CONFIG_PCIE2 1 /* PCIE controller 2 */ 28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 31 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 32 33 /* 34 * Multicore config 35 */ 36 #define CONFIG_MP 37 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ 38 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ 39 40 /* 41 * DDR config 42 */ 43 #undef CONFIG_FSL_DDR_INTERACTIVE 44 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 45 #define CONFIG_DDR_SPD 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 48 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 49 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 50 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 51 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 52 #define CONFIG_DDR_ECC 53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 54 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 56 #define CONFIG_VERY_BIG_RAM 57 58 #ifndef __ASSEMBLY__ 59 extern unsigned long get_board_sys_clk(unsigned long dummy); 60 extern unsigned long get_board_ddr_clk(unsigned long dummy); 61 #endif 62 63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 #define CONFIG_ENABLE_36BIT_PHYS 1 72 73 #define CONFIG_SYS_CCSRBAR 0xef000000 74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 75 76 /* 77 * Diagnostics 78 */ 79 #define CONFIG_SYS_ALT_MEMTEST 80 #define CONFIG_SYS_MEMTEST_START 0x10000000 81 #define CONFIG_SYS_MEMTEST_END 0x20000000 82 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 83 CONFIG_SYS_POST_I2C) 84 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \ 85 CONFIG_SYS_I2C_DS4510_ADDR, \ 86 CONFIG_SYS_I2C_EEPROM_ADDR, \ 87 CONFIG_SYS_I2C_LM90_ADDR, \ 88 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 89 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 90 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 91 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 92 CONFIG_SYS_I2C_PEX8518_ADDR, \ 93 CONFIG_SYS_I2C_RTC_ADDR} 94 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ 95 #define I2C_ADDR_IGNORE_LIST {0x50} 96 97 /* 98 * Memory map 99 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 100 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 101 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 102 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 103 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 104 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 105 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable 106 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 107 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 108 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 109 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 110 */ 111 112 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 113 114 /* 115 * NAND flash configuration 116 */ 117 #define CONFIG_SYS_NAND_BASE 0xef800000 118 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 119 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ 120 CONFIG_SYS_NAND_BASE2} 121 #define CONFIG_SYS_MAX_NAND_DEVICE 2 122 #define CONFIG_NAND_FSL_ELBC 123 124 /* 125 * NOR flash configuration 126 */ 127 #define CONFIG_SYS_FLASH_BASE 0xf8000000 128 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 129 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 130 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 131 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 132 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 133 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 134 #define CONFIG_FLASH_CFI_DRIVER 135 #define CONFIG_SYS_FLASH_CFI 136 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 137 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 138 {0xf7f40000, 0xc0000} } 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 140 141 /* 142 * Chip select configuration 143 */ 144 /* NOR Flash 0 on CS0 */ 145 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 146 BR_PS_16 | \ 147 BR_V) 148 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ 149 OR_GPCM_CSNT | \ 150 OR_GPCM_XACS | \ 151 OR_GPCM_ACS_DIV2 | \ 152 OR_GPCM_SCY_8 | \ 153 OR_GPCM_TRLX | \ 154 OR_GPCM_EHTR | \ 155 OR_GPCM_EAD) 156 157 /* NOR Flash 1 on CS1 */ 158 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 159 BR_PS_16 | \ 160 BR_V) 161 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 162 163 /* NAND flash on CS2 */ 164 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 165 (2<<BR_DECC_SHIFT) | \ 166 BR_PS_8 | \ 167 BR_MS_FCM | \ 168 BR_V) 169 170 /* NAND flash on CS2 */ 171 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 172 OR_FCM_PGS | \ 173 OR_FCM_CSCT | \ 174 OR_FCM_CST | \ 175 OR_FCM_CHT | \ 176 OR_FCM_SCY_1 | \ 177 OR_FCM_TRLX | \ 178 OR_FCM_EHTR) 179 180 /* NAND flash on CS3 */ 181 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 182 (2<<BR_DECC_SHIFT) | \ 183 BR_PS_8 | \ 184 BR_MS_FCM | \ 185 BR_V) 186 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 187 188 /* 189 * Use L1 as initial stack 190 */ 191 #define CONFIG_SYS_INIT_RAM_LOCK 1 192 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 193 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 194 195 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 196 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 197 198 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 199 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 200 201 /* 202 * Serial Port 203 */ 204 #define CONFIG_CONS_INDEX 1 205 #define CONFIG_SYS_NS16550_SERIAL 206 #define CONFIG_SYS_NS16550_REG_SIZE 1 207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 208 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 209 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 210 #define CONFIG_SYS_BAUDRATE_TABLE \ 211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 212 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 213 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 214 215 /* 216 * I2C 217 */ 218 #define CONFIG_SYS_I2C 219 #define CONFIG_SYS_I2C_FSL 220 #define CONFIG_SYS_FSL_I2C_SPEED 400000 221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 222 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 223 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 224 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 225 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 226 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 227 228 /* PEX8518 slave I2C interface */ 229 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 230 231 /* I2C DS1631 temperature sensor */ 232 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 233 #define CONFIG_DTT_DS1621 234 #define CONFIG_DTT_SENSORS { 0 } 235 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 236 237 /* I2C EEPROM - AT24C128B */ 238 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 239 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 242 243 /* I2C RTC */ 244 #define CONFIG_RTC_M41T11 1 245 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 246 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 247 248 /* GPIO/EEPROM/SRAM */ 249 #define CONFIG_DS4510 250 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 251 252 /* GPIO */ 253 #define CONFIG_PCA953X 254 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 255 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 256 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 257 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 258 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 259 260 /* 261 * PU = pulled high, PD = pulled low 262 * I = input, O = output, IO = input/output 263 */ 264 /* PCA9557 @ 0x18*/ 265 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 266 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 267 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 268 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 269 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 270 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 271 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ 272 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ 273 274 /* PCA9557 @ 0x1c*/ 275 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 276 #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ 277 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 278 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 279 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 280 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 281 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 282 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 283 284 /* PCA9557 @ 0x1e*/ 285 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 286 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 287 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 288 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 289 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 290 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ 291 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ 292 293 /* PCA9557 @ 0x1f */ 294 #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ 295 #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ 296 #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ 297 #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ 298 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ 299 300 /* 301 * General PCI 302 * Memory space is mapped 1-1, but I/O space must start from 0. 303 */ 304 /* PCIE1 - VPX P1 */ 305 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 306 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 307 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 308 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 309 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 310 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 311 312 /* PCIE2 - PEX8518 */ 313 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 314 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 315 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 316 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 317 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 318 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 319 320 /* 321 * Networking options 322 */ 323 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 324 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 325 #define CONFIG_TSEC_TBI 326 #define CONFIG_MII 1 /* MII PHY management */ 327 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 328 #define CONFIG_ETHPRIME "eTSEC2" 329 330 /* 331 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force 332 * 1000mbps SGMII link 333 */ 334 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 335 TBICR_PHY_RESET \ 336 | TBICR_FULL_DUPLEX \ 337 | TBICR_SPEED1_SET \ 338 ) 339 340 #define CONFIG_TSEC1 1 341 #define CONFIG_TSEC1_NAME "eTSEC1" 342 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 343 #define TSEC1_PHY_ADDR 1 344 #define TSEC1_PHYIDX 0 345 #define CONFIG_HAS_ETH0 346 347 #define CONFIG_TSEC2 1 348 #define CONFIG_TSEC2_NAME "eTSEC2" 349 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 350 #define TSEC2_PHY_ADDR 2 351 #define TSEC2_PHYIDX 0 352 #define CONFIG_HAS_ETH1 353 354 /* 355 * Command configuration. 356 */ 357 #define CONFIG_CMD_DATE 358 #define CONFIG_CMD_DS4510 359 #define CONFIG_CMD_DS4510_INFO 360 #define CONFIG_CMD_DTT 361 #define CONFIG_CMD_EEPROM 362 #define CONFIG_CMD_JFFS2 363 #define CONFIG_CMD_NAND 364 #define CONFIG_CMD_PCA953X 365 #define CONFIG_CMD_PCA953X_INFO 366 #define CONFIG_CMD_PCI 367 #define CONFIG_CMD_PCI_ENUM 368 #define CONFIG_CMD_REGINFO 369 370 /* 371 * Miscellaneous configurable options 372 */ 373 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 374 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 375 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 376 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 377 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 378 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 379 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 380 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 381 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 382 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 383 #define CONFIG_PREBOOT /* enable preboot variable */ 384 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 385 386 /* 387 * For booting Linux, the board info and command line data 388 * have to be in the first 16 MB of memory, since this is 389 * the maximum mapped by the Linux kernel during initialization. 390 */ 391 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 392 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 393 394 /* 395 * Environment Configuration 396 */ 397 #define CONFIG_ENV_IS_IN_FLASH 1 398 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 399 #define CONFIG_ENV_SIZE 0x8000 400 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 401 402 /* 403 * Flash memory map: 404 * fff80000 - ffffffff Pri U-Boot (512 KB) 405 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 406 * fff00000 - fff3ffff Pri FDT (256KB) 407 * fef00000 - ffefffff Pri OS image (16MB) 408 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 409 * 410 * f7f80000 - f7ffffff Sec U-Boot (512 KB) 411 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) 412 * f7f00000 - f7f3ffff Sec FDT (256KB) 413 * f6f00000 - f7efffff Sec OS image (16MB) 414 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 415 */ 416 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 417 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) 418 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 419 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) 420 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 421 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 422 423 #define CONFIG_PROG_UBOOT1 \ 424 "$download_cmd $loadaddr $ubootfile; " \ 425 "if test $? -eq 0; then " \ 426 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 427 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 428 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 429 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 430 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 431 "if test $? -ne 0; then " \ 432 "echo PROGRAM FAILED; " \ 433 "else; " \ 434 "echo PROGRAM SUCCEEDED; " \ 435 "fi; " \ 436 "else; " \ 437 "echo DOWNLOAD FAILED; " \ 438 "fi;" 439 440 #define CONFIG_PROG_UBOOT2 \ 441 "$download_cmd $loadaddr $ubootfile; " \ 442 "if test $? -eq 0; then " \ 443 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 444 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 445 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 446 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 447 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 448 "if test $? -ne 0; then " \ 449 "echo PROGRAM FAILED; " \ 450 "else; " \ 451 "echo PROGRAM SUCCEEDED; " \ 452 "fi; " \ 453 "else; " \ 454 "echo DOWNLOAD FAILED; " \ 455 "fi;" 456 457 #define CONFIG_BOOT_OS_NET \ 458 "$download_cmd $osaddr $osfile; " \ 459 "if test $? -eq 0; then " \ 460 "if test -n $fdtaddr; then " \ 461 "$download_cmd $fdtaddr $fdtfile; " \ 462 "if test $? -eq 0; then " \ 463 "bootm $osaddr - $fdtaddr; " \ 464 "else; " \ 465 "echo FDT DOWNLOAD FAILED; " \ 466 "fi; " \ 467 "else; " \ 468 "bootm $osaddr; " \ 469 "fi; " \ 470 "else; " \ 471 "echo OS DOWNLOAD FAILED; " \ 472 "fi;" 473 474 #define CONFIG_PROG_OS1 \ 475 "$download_cmd $osaddr $osfile; " \ 476 "if test $? -eq 0; then " \ 477 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 478 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 479 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 480 "if test $? -ne 0; then " \ 481 "echo OS PROGRAM FAILED; " \ 482 "else; " \ 483 "echo OS PROGRAM SUCCEEDED; " \ 484 "fi; " \ 485 "else; " \ 486 "echo OS DOWNLOAD FAILED; " \ 487 "fi;" 488 489 #define CONFIG_PROG_OS2 \ 490 "$download_cmd $osaddr $osfile; " \ 491 "if test $? -eq 0; then " \ 492 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 493 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 494 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 495 "if test $? -ne 0; then " \ 496 "echo OS PROGRAM FAILED; " \ 497 "else; " \ 498 "echo OS PROGRAM SUCCEEDED; " \ 499 "fi; " \ 500 "else; " \ 501 "echo OS DOWNLOAD FAILED; " \ 502 "fi;" 503 504 #define CONFIG_PROG_FDT1 \ 505 "$download_cmd $fdtaddr $fdtfile; " \ 506 "if test $? -eq 0; then " \ 507 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 508 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 509 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 510 "if test $? -ne 0; then " \ 511 "echo FDT PROGRAM FAILED; " \ 512 "else; " \ 513 "echo FDT PROGRAM SUCCEEDED; " \ 514 "fi; " \ 515 "else; " \ 516 "echo FDT DOWNLOAD FAILED; " \ 517 "fi;" 518 519 #define CONFIG_PROG_FDT2 \ 520 "$download_cmd $fdtaddr $fdtfile; " \ 521 "if test $? -eq 0; then " \ 522 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 523 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 524 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 525 "if test $? -ne 0; then " \ 526 "echo FDT PROGRAM FAILED; " \ 527 "else; " \ 528 "echo FDT PROGRAM SUCCEEDED; " \ 529 "fi; " \ 530 "else; " \ 531 "echo FDT DOWNLOAD FAILED; " \ 532 "fi;" 533 534 #define CONFIG_EXTRA_ENV_SETTINGS \ 535 "autoload=yes\0" \ 536 "download_cmd=tftp\0" \ 537 "console_args=console=ttyS0,115200\0" \ 538 "root_args=root=/dev/nfs rw\0" \ 539 "misc_args=ip=on\0" \ 540 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 541 "bootfile=/home/user/file\0" \ 542 "osfile=/home/user/board.uImage\0" \ 543 "fdtfile=/home/user/board.dtb\0" \ 544 "ubootfile=/home/user/u-boot.bin\0" \ 545 "fdtaddr=0x1e00000\0" \ 546 "osaddr=0x1000000\0" \ 547 "loadaddr=0x1000000\0" \ 548 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 549 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 550 "prog_os1="CONFIG_PROG_OS1"\0" \ 551 "prog_os2="CONFIG_PROG_OS2"\0" \ 552 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 553 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 554 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 555 "bootcmd_flash1=run set_bootargs; " \ 556 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 557 "bootcmd_flash2=run set_bootargs; " \ 558 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 559 "bootcmd=run bootcmd_flash1\0" 560 #endif /* __CONFIG_H */ 561