1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite537x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_SYS_BOARD_NAME	"XPedite5370"
18 #define CONFIG_SYS_FORM_3U_VPX	1
19 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
20 
21 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
22 #define CONFIG_PCIE1		1	/* PCIE controller 1 */
23 #define CONFIG_PCIE2		1	/* PCIE controller 2 */
24 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
25 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
26 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
27 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
28 
29 /*
30  * Multicore config
31  */
32 #define CONFIG_MP
33 #define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
34 #define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
35 
36 /*
37  * DDR config
38  */
39 #undef CONFIG_FSL_DDR_INTERACTIVE
40 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
41 #define CONFIG_DDR_SPD
42 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
43 #define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
44 #define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
45 #define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
46 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
47 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
48 #define CONFIG_DDR_ECC
49 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
50 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
51 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
52 #define CONFIG_VERY_BIG_RAM
53 
54 #ifndef __ASSEMBLY__
55 extern unsigned long get_board_sys_clk(unsigned long dummy);
56 extern unsigned long get_board_ddr_clk(unsigned long dummy);
57 #endif
58 
59 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
60 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
61 
62 /*
63  * These can be toggled for performance analysis, otherwise use default.
64  */
65 #define CONFIG_L2_CACHE			/* toggle L2 cache */
66 #define CONFIG_BTB			/* toggle branch predition */
67 #define CONFIG_ENABLE_36BIT_PHYS	1
68 
69 #define CONFIG_SYS_CCSRBAR		0xef000000
70 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
71 
72 /*
73  * Diagnostics
74  */
75 #define CONFIG_SYS_ALT_MEMTEST
76 #define CONFIG_SYS_MEMTEST_START	0x10000000
77 #define CONFIG_SYS_MEMTEST_END		0x20000000
78 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
79 					 CONFIG_SYS_POST_I2C)
80 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
81 #define I2C_ADDR_IGNORE_LIST		{0x50}
82 
83 /*
84  * Memory map
85  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
86  * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
87  * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
88  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
89  * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
90  * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
91  * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
92  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
93  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
94  * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
95  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
96  */
97 
98 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
99 
100 /*
101  * NAND flash configuration
102  */
103 #define CONFIG_SYS_NAND_BASE		0xef800000
104 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
105 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
106 					 CONFIG_SYS_NAND_BASE2}
107 #define CONFIG_SYS_MAX_NAND_DEVICE	2
108 #define CONFIG_NAND_FSL_ELBC
109 
110 /*
111  * NOR flash configuration
112  */
113 #define CONFIG_SYS_FLASH_BASE		0xf8000000
114 #define CONFIG_SYS_FLASH_BASE2		0xf0000000
115 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
116 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
117 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
118 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
119 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
120 #define CONFIG_FLASH_CFI_DRIVER
121 #define CONFIG_SYS_FLASH_CFI
122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
123 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
124 						  {0xf7f40000, 0xc0000} }
125 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
126 
127 /*
128  * Chip select configuration
129  */
130 /* NOR Flash 0 on CS0 */
131 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
132 				 BR_PS_16		| \
133 				 BR_V)
134 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
135 				 OR_GPCM_CSNT		| \
136 				 OR_GPCM_XACS		| \
137 				 OR_GPCM_ACS_DIV2	| \
138 				 OR_GPCM_SCY_8		| \
139 				 OR_GPCM_TRLX		| \
140 				 OR_GPCM_EHTR		| \
141 				 OR_GPCM_EAD)
142 
143 /* NOR Flash 1 on CS1 */
144 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
145 				 BR_PS_16		| \
146 				 BR_V)
147 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
148 
149 /* NAND flash on CS2 */
150 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
151 				 (2<<BR_DECC_SHIFT)	| \
152 				 BR_PS_8		| \
153 				 BR_MS_FCM		| \
154 				 BR_V)
155 
156 /* NAND flash on CS2 */
157 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
158 				 OR_FCM_PGS	| \
159 				 OR_FCM_CSCT	| \
160 				 OR_FCM_CST	| \
161 				 OR_FCM_CHT	| \
162 				 OR_FCM_SCY_1	| \
163 				 OR_FCM_TRLX	| \
164 				 OR_FCM_EHTR)
165 
166 /* NAND flash on CS3 */
167 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
168 				 (2<<BR_DECC_SHIFT)	| \
169 				 BR_PS_8		| \
170 				 BR_MS_FCM		| \
171 				 BR_V)
172 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
173 
174 /*
175  * Use L1 as initial stack
176  */
177 #define CONFIG_SYS_INIT_RAM_LOCK	1
178 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
179 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
180 
181 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
182 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
183 
184 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
185 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
186 
187 /*
188  * Serial Port
189  */
190 #define CONFIG_CONS_INDEX		1
191 #define CONFIG_SYS_NS16550_SERIAL
192 #define CONFIG_SYS_NS16550_REG_SIZE	1
193 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
194 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
195 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
196 #define CONFIG_SYS_BAUDRATE_TABLE	\
197 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
198 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
199 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
200 
201 /*
202  * I2C
203  */
204 #define CONFIG_SYS_I2C
205 #define CONFIG_SYS_I2C_FSL
206 #define CONFIG_SYS_FSL_I2C_SPEED	400000
207 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
208 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
209 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
210 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
211 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
212 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
213 
214 /* PEX8518 slave I2C interface */
215 #define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
216 
217 /* I2C DS1631 temperature sensor */
218 #define CONFIG_SYS_I2C_LM90_ADDR	0x4c
219 
220 /* I2C EEPROM - AT24C128B */
221 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
222 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
225 
226 /* I2C RTC */
227 #define CONFIG_RTC_M41T11		1
228 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
229 #define CONFIG_SYS_M41T11_BASE_YEAR	2000
230 
231 /* GPIO */
232 #define CONFIG_PCA953X
233 #define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
234 #define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
235 #define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
236 #define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
237 #define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
238 
239 /*
240  * PU = pulled high, PD = pulled low
241  * I = input, O = output, IO = input/output
242  */
243 /* PCA9557 @ 0x18*/
244 #define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
245 #define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
246 #define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
247 #define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
248 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
249 #define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
250 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
251 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
252 
253 /* PCA9557 @ 0x1c*/
254 #define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
255 #define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
256 #define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
257 #define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
258 #define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
259 #define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
260 #define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
261 #define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
262 
263 /* PCA9557 @ 0x1e*/
264 #define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
265 #define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
266 #define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
267 #define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
268 #define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
269 #define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
270 #define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
271 
272 /* PCA9557 @ 0x1f */
273 #define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
274 #define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
275 #define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
276 #define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
277 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
278 
279 /*
280  * General PCI
281  * Memory space is mapped 1-1, but I/O space must start from 0.
282  */
283 /* PCIE1 - VPX P1 */
284 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
285 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
286 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
287 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
288 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
289 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
290 
291 /* PCIE2 - PEX8518 */
292 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
293 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
294 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
295 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
296 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
297 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
298 
299 /*
300  * Networking options
301  */
302 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
303 #define CONFIG_TSEC_TBI
304 #define CONFIG_MII		1	/* MII PHY management */
305 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
306 #define CONFIG_ETHPRIME		"eTSEC2"
307 
308 /*
309  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
310  * 1000mbps SGMII link
311  */
312 #define CONFIG_TSEC_TBICR_SETTINGS ( \
313 		TBICR_PHY_RESET \
314 		| TBICR_FULL_DUPLEX \
315 		| TBICR_SPEED1_SET \
316 		)
317 
318 #define CONFIG_TSEC1		1
319 #define CONFIG_TSEC1_NAME	"eTSEC1"
320 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
321 #define TSEC1_PHY_ADDR		1
322 #define TSEC1_PHYIDX		0
323 #define CONFIG_HAS_ETH0
324 
325 #define CONFIG_TSEC2		1
326 #define CONFIG_TSEC2_NAME	"eTSEC2"
327 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
328 #define TSEC2_PHY_ADDR		2
329 #define TSEC2_PHYIDX		0
330 #define CONFIG_HAS_ETH1
331 
332 /*
333  * Miscellaneous configurable options
334  */
335 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
336 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
337 #define CONFIG_PREBOOT				/* enable preboot variable */
338 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
339 
340 /*
341  * For booting Linux, the board info and command line data
342  * have to be in the first 16 MB of memory, since this is
343  * the maximum mapped by the Linux kernel during initialization.
344  */
345 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
346 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
347 
348 /*
349  * Environment Configuration
350  */
351 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
352 #define CONFIG_ENV_SIZE		0x8000
353 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
354 
355 /*
356  * Flash memory map:
357  * fff80000 - ffffffff     Pri U-Boot (512 KB)
358  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
359  * fff00000 - fff3ffff     Pri FDT (256KB)
360  * fef00000 - ffefffff     Pri OS image (16MB)
361  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
362  *
363  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
364  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
365  * f7f00000 - f7f3ffff     Sec FDT (256KB)
366  * f6f00000 - f7efffff     Sec OS image (16MB)
367  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
368  */
369 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
370 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
371 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
372 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
373 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
374 #define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
375 
376 #define CONFIG_PROG_UBOOT1						\
377 	"$download_cmd $loadaddr $ubootfile; "				\
378 	"if test $? -eq 0; then "					\
379 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
380 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
381 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
382 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
383 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
384 		"if test $? -ne 0; then "				\
385 			"echo PROGRAM FAILED; "				\
386 		"else; "						\
387 			"echo PROGRAM SUCCEEDED; "			\
388 		"fi; "							\
389 	"else; "							\
390 		"echo DOWNLOAD FAILED; "				\
391 	"fi;"
392 
393 #define CONFIG_PROG_UBOOT2						\
394 	"$download_cmd $loadaddr $ubootfile; "				\
395 	"if test $? -eq 0; then "					\
396 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
397 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
398 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
399 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
400 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
401 		"if test $? -ne 0; then "				\
402 			"echo PROGRAM FAILED; "				\
403 		"else; "						\
404 			"echo PROGRAM SUCCEEDED; "			\
405 		"fi; "							\
406 	"else; "							\
407 		"echo DOWNLOAD FAILED; "				\
408 	"fi;"
409 
410 #define CONFIG_BOOT_OS_NET						\
411 	"$download_cmd $osaddr $osfile; "				\
412 	"if test $? -eq 0; then "					\
413 		"if test -n $fdtaddr; then "				\
414 			"$download_cmd $fdtaddr $fdtfile; "		\
415 			"if test $? -eq 0; then "			\
416 				"bootm $osaddr - $fdtaddr; "		\
417 			"else; "					\
418 				"echo FDT DOWNLOAD FAILED; "		\
419 			"fi; "						\
420 		"else; "						\
421 			"bootm $osaddr; "				\
422 		"fi; "							\
423 	"else; "							\
424 		"echo OS DOWNLOAD FAILED; "				\
425 	"fi;"
426 
427 #define CONFIG_PROG_OS1							\
428 	"$download_cmd $osaddr $osfile; "				\
429 	"if test $? -eq 0; then "					\
430 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
431 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
432 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
433 		"if test $? -ne 0; then "				\
434 			"echo OS PROGRAM FAILED; "			\
435 		"else; "						\
436 			"echo OS PROGRAM SUCCEEDED; "			\
437 		"fi; "							\
438 	"else; "							\
439 		"echo OS DOWNLOAD FAILED; "				\
440 	"fi;"
441 
442 #define CONFIG_PROG_OS2							\
443 	"$download_cmd $osaddr $osfile; "				\
444 	"if test $? -eq 0; then "					\
445 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
446 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
447 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
448 		"if test $? -ne 0; then "				\
449 			"echo OS PROGRAM FAILED; "			\
450 		"else; "						\
451 			"echo OS PROGRAM SUCCEEDED; "			\
452 		"fi; "							\
453 	"else; "							\
454 		"echo OS DOWNLOAD FAILED; "				\
455 	"fi;"
456 
457 #define CONFIG_PROG_FDT1						\
458 	"$download_cmd $fdtaddr $fdtfile; "				\
459 	"if test $? -eq 0; then "					\
460 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
461 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
462 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
463 		"if test $? -ne 0; then "				\
464 			"echo FDT PROGRAM FAILED; "			\
465 		"else; "						\
466 			"echo FDT PROGRAM SUCCEEDED; "			\
467 		"fi; "							\
468 	"else; "							\
469 		"echo FDT DOWNLOAD FAILED; "				\
470 	"fi;"
471 
472 #define CONFIG_PROG_FDT2						\
473 	"$download_cmd $fdtaddr $fdtfile; "				\
474 	"if test $? -eq 0; then "					\
475 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
476 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
477 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
478 		"if test $? -ne 0; then "				\
479 			"echo FDT PROGRAM FAILED; "			\
480 		"else; "						\
481 			"echo FDT PROGRAM SUCCEEDED; "			\
482 		"fi; "							\
483 	"else; "							\
484 		"echo FDT DOWNLOAD FAILED; "				\
485 	"fi;"
486 
487 #define	CONFIG_EXTRA_ENV_SETTINGS					\
488 	"autoload=yes\0"						\
489 	"download_cmd=tftp\0"						\
490 	"console_args=console=ttyS0,115200\0"				\
491 	"root_args=root=/dev/nfs rw\0"					\
492 	"misc_args=ip=on\0"						\
493 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
494 	"bootfile=/home/user/file\0"					\
495 	"osfile=/home/user/board.uImage\0"				\
496 	"fdtfile=/home/user/board.dtb\0"				\
497 	"ubootfile=/home/user/u-boot.bin\0"				\
498 	"fdtaddr=0x1e00000\0"						\
499 	"osaddr=0x1000000\0"						\
500 	"loadaddr=0x1000000\0"						\
501 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
502 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
503 	"prog_os1="CONFIG_PROG_OS1"\0"					\
504 	"prog_os2="CONFIG_PROG_OS2"\0"					\
505 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
506 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
507 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
508 	"bootcmd_flash1=run set_bootargs; "				\
509 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
510 	"bootcmd_flash2=run set_bootargs; "				\
511 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
512 	"bootcmd=run bootcmd_flash1\0"
513 #endif	/* __CONFIG_H */
514