1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite537x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_SYS_BOARD_NAME	"XPedite5370"
18 #define CONFIG_SYS_FORM_3U_VPX	1
19 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
20 
21 #ifndef CONFIG_SYS_TEXT_BASE
22 #define CONFIG_SYS_TEXT_BASE	0xfff80000
23 #endif
24 
25 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
26 #define CONFIG_PCIE1		1	/* PCIE controller 1 */
27 #define CONFIG_PCIE2		1	/* PCIE controller 2 */
28 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
29 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
30 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
31 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
32 #define CONFIG_FSL_ELBC		1
33 
34 /*
35  * Multicore config
36  */
37 #define CONFIG_MP
38 #define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
39 #define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
40 
41 /*
42  * DDR config
43  */
44 #undef CONFIG_FSL_DDR_INTERACTIVE
45 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
46 #define CONFIG_DDR_SPD
47 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
48 #define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
49 #define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
50 #define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
51 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
52 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
53 #define CONFIG_DDR_ECC
54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
55 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
56 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
57 #define CONFIG_VERY_BIG_RAM
58 
59 #ifndef __ASSEMBLY__
60 extern unsigned long get_board_sys_clk(unsigned long dummy);
61 extern unsigned long get_board_ddr_clk(unsigned long dummy);
62 #endif
63 
64 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
65 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
66 
67 /*
68  * These can be toggled for performance analysis, otherwise use default.
69  */
70 #define CONFIG_L2_CACHE			/* toggle L2 cache */
71 #define CONFIG_BTB			/* toggle branch predition */
72 #define CONFIG_ENABLE_36BIT_PHYS	1
73 
74 #define CONFIG_SYS_CCSRBAR		0xef000000
75 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
76 
77 /*
78  * Diagnostics
79  */
80 #define CONFIG_SYS_ALT_MEMTEST
81 #define CONFIG_SYS_MEMTEST_START	0x10000000
82 #define CONFIG_SYS_MEMTEST_END		0x20000000
83 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
84 					 CONFIG_SYS_POST_I2C)
85 #define I2C_ADDR_LIST			{CONFIG_SYS_I2C_DS1621_ADDR,	\
86 					 CONFIG_SYS_I2C_DS4510_ADDR,	\
87 					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
88 					 CONFIG_SYS_I2C_LM90_ADDR,	\
89 					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
90 					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
91 					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
92 					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
93 					 CONFIG_SYS_I2C_PEX8518_ADDR,	\
94 					 CONFIG_SYS_I2C_RTC_ADDR}
95 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
96 #define I2C_ADDR_IGNORE_LIST		{0x50}
97 
98 /*
99  * Memory map
100  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
101  * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
102  * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
103  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
104  * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
105  * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
106  * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
107  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
108  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
109  * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
110  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
111  */
112 
113 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
114 
115 /*
116  * NAND flash configuration
117  */
118 #define CONFIG_SYS_NAND_BASE		0xef800000
119 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
120 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
121 					 CONFIG_SYS_NAND_BASE2}
122 #define CONFIG_SYS_MAX_NAND_DEVICE	2
123 #define CONFIG_NAND_FSL_ELBC
124 
125 /*
126  * NOR flash configuration
127  */
128 #define CONFIG_SYS_FLASH_BASE		0xf8000000
129 #define CONFIG_SYS_FLASH_BASE2		0xf0000000
130 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
131 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
132 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
133 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
134 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
135 #define CONFIG_FLASH_CFI_DRIVER
136 #define CONFIG_SYS_FLASH_CFI
137 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
138 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
139 						  {0xf7f40000, 0xc0000} }
140 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
141 
142 /*
143  * Chip select configuration
144  */
145 /* NOR Flash 0 on CS0 */
146 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
147 				 BR_PS_16		| \
148 				 BR_V)
149 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
150 				 OR_GPCM_CSNT		| \
151 				 OR_GPCM_XACS		| \
152 				 OR_GPCM_ACS_DIV2	| \
153 				 OR_GPCM_SCY_8		| \
154 				 OR_GPCM_TRLX		| \
155 				 OR_GPCM_EHTR		| \
156 				 OR_GPCM_EAD)
157 
158 /* NOR Flash 1 on CS1 */
159 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
160 				 BR_PS_16		| \
161 				 BR_V)
162 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
163 
164 /* NAND flash on CS2 */
165 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
166 				 (2<<BR_DECC_SHIFT)	| \
167 				 BR_PS_8		| \
168 				 BR_MS_FCM		| \
169 				 BR_V)
170 
171 /* NAND flash on CS2 */
172 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
173 				 OR_FCM_PGS	| \
174 				 OR_FCM_CSCT	| \
175 				 OR_FCM_CST	| \
176 				 OR_FCM_CHT	| \
177 				 OR_FCM_SCY_1	| \
178 				 OR_FCM_TRLX	| \
179 				 OR_FCM_EHTR)
180 
181 /* NAND flash on CS3 */
182 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
183 				 (2<<BR_DECC_SHIFT)	| \
184 				 BR_PS_8		| \
185 				 BR_MS_FCM		| \
186 				 BR_V)
187 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
188 
189 /*
190  * Use L1 as initial stack
191  */
192 #define CONFIG_SYS_INIT_RAM_LOCK	1
193 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
194 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
195 
196 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
197 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
198 
199 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
200 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
201 
202 /*
203  * Serial Port
204  */
205 #define CONFIG_CONS_INDEX		1
206 #define CONFIG_SYS_NS16550_SERIAL
207 #define CONFIG_SYS_NS16550_REG_SIZE	1
208 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
209 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
210 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
211 #define CONFIG_SYS_BAUDRATE_TABLE	\
212 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
213 #define CONFIG_BAUDRATE			115200
214 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
215 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
216 
217 /*
218  * I2C
219  */
220 #define CONFIG_SYS_I2C
221 #define CONFIG_SYS_I2C_FSL
222 #define CONFIG_SYS_FSL_I2C_SPEED	400000
223 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
224 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
225 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
226 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
227 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
228 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
229 
230 /* PEX8518 slave I2C interface */
231 #define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
232 
233 /* I2C DS1631 temperature sensor */
234 #define CONFIG_SYS_I2C_DS1621_ADDR	0x48
235 #define CONFIG_DTT_DS1621
236 #define CONFIG_DTT_SENSORS		{ 0 }
237 #define CONFIG_SYS_I2C_LM90_ADDR	0x4c
238 
239 /* I2C EEPROM - AT24C128B */
240 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
241 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
242 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
244 
245 /* I2C RTC */
246 #define CONFIG_RTC_M41T11		1
247 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
248 #define CONFIG_SYS_M41T11_BASE_YEAR	2000
249 
250 /* GPIO/EEPROM/SRAM */
251 #define CONFIG_DS4510
252 #define CONFIG_SYS_I2C_DS4510_ADDR	0x51
253 
254 /* GPIO */
255 #define CONFIG_PCA953X
256 #define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
257 #define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
258 #define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
259 #define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
260 #define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
261 
262 /*
263  * PU = pulled high, PD = pulled low
264  * I = input, O = output, IO = input/output
265  */
266 /* PCA9557 @ 0x18*/
267 #define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
268 #define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
269 #define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
270 #define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
271 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
272 #define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
273 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
274 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
275 
276 /* PCA9557 @ 0x1c*/
277 #define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
278 #define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
279 #define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
280 #define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
281 #define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
282 #define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
283 #define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
284 #define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
285 
286 /* PCA9557 @ 0x1e*/
287 #define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
288 #define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
289 #define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
290 #define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
291 #define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
292 #define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
293 #define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
294 
295 /* PCA9557 @ 0x1f */
296 #define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
297 #define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
298 #define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
299 #define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
300 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
301 
302 /*
303  * General PCI
304  * Memory space is mapped 1-1, but I/O space must start from 0.
305  */
306 /* PCIE1 - VPX P1 */
307 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
308 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
309 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
310 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
311 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
312 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
313 
314 /* PCIE2 - PEX8518 */
315 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
316 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
317 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
318 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
319 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
320 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
321 
322 /*
323  * Networking options
324  */
325 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
326 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
327 #define CONFIG_TSEC_TBI
328 #define CONFIG_MII		1	/* MII PHY management */
329 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
330 #define CONFIG_ETHPRIME		"eTSEC2"
331 
332 /*
333  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
334  * 1000mbps SGMII link
335  */
336 #define CONFIG_TSEC_TBICR_SETTINGS ( \
337 		TBICR_PHY_RESET \
338 		| TBICR_FULL_DUPLEX \
339 		| TBICR_SPEED1_SET \
340 		)
341 
342 #define CONFIG_TSEC1		1
343 #define CONFIG_TSEC1_NAME	"eTSEC1"
344 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
345 #define TSEC1_PHY_ADDR		1
346 #define TSEC1_PHYIDX		0
347 #define CONFIG_HAS_ETH0
348 
349 #define CONFIG_TSEC2		1
350 #define CONFIG_TSEC2_NAME	"eTSEC2"
351 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
352 #define TSEC2_PHY_ADDR		2
353 #define TSEC2_PHYIDX		0
354 #define CONFIG_HAS_ETH1
355 
356 /*
357  * Command configuration.
358  */
359 #define CONFIG_CMD_DATE
360 #define CONFIG_CMD_DS4510
361 #define CONFIG_CMD_DS4510_INFO
362 #define CONFIG_CMD_DTT
363 #define CONFIG_CMD_EEPROM
364 #define CONFIG_CMD_JFFS2
365 #define CONFIG_CMD_NAND
366 #define CONFIG_CMD_PCA953X
367 #define CONFIG_CMD_PCA953X_INFO
368 #define CONFIG_CMD_PCI
369 #define CONFIG_CMD_PCI_ENUM
370 #define CONFIG_CMD_REGINFO
371 
372 /*
373  * Miscellaneous configurable options
374  */
375 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
376 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
377 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
378 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
379 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
380 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
381 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
382 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
383 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
384 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
385 #define CONFIG_PREBOOT				/* enable preboot variable */
386 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
387 
388 /*
389  * For booting Linux, the board info and command line data
390  * have to be in the first 16 MB of memory, since this is
391  * the maximum mapped by the Linux kernel during initialization.
392  */
393 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
394 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
395 
396 /*
397  * Environment Configuration
398  */
399 #define CONFIG_ENV_IS_IN_FLASH	1
400 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
401 #define CONFIG_ENV_SIZE		0x8000
402 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
403 
404 /*
405  * Flash memory map:
406  * fff80000 - ffffffff     Pri U-Boot (512 KB)
407  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
408  * fff00000 - fff3ffff     Pri FDT (256KB)
409  * fef00000 - ffefffff     Pri OS image (16MB)
410  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
411  *
412  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
413  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
414  * f7f00000 - f7f3ffff     Sec FDT (256KB)
415  * f6f00000 - f7efffff     Sec OS image (16MB)
416  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
417  */
418 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
419 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
420 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
421 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
422 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
423 #define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
424 
425 #define CONFIG_PROG_UBOOT1						\
426 	"$download_cmd $loadaddr $ubootfile; "				\
427 	"if test $? -eq 0; then "					\
428 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
429 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
430 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
431 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
432 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
433 		"if test $? -ne 0; then "				\
434 			"echo PROGRAM FAILED; "				\
435 		"else; "						\
436 			"echo PROGRAM SUCCEEDED; "			\
437 		"fi; "							\
438 	"else; "							\
439 		"echo DOWNLOAD FAILED; "				\
440 	"fi;"
441 
442 #define CONFIG_PROG_UBOOT2						\
443 	"$download_cmd $loadaddr $ubootfile; "				\
444 	"if test $? -eq 0; then "					\
445 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
446 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
447 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
448 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
449 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
450 		"if test $? -ne 0; then "				\
451 			"echo PROGRAM FAILED; "				\
452 		"else; "						\
453 			"echo PROGRAM SUCCEEDED; "			\
454 		"fi; "							\
455 	"else; "							\
456 		"echo DOWNLOAD FAILED; "				\
457 	"fi;"
458 
459 #define CONFIG_BOOT_OS_NET						\
460 	"$download_cmd $osaddr $osfile; "				\
461 	"if test $? -eq 0; then "					\
462 		"if test -n $fdtaddr; then "				\
463 			"$download_cmd $fdtaddr $fdtfile; "		\
464 			"if test $? -eq 0; then "			\
465 				"bootm $osaddr - $fdtaddr; "		\
466 			"else; "					\
467 				"echo FDT DOWNLOAD FAILED; "		\
468 			"fi; "						\
469 		"else; "						\
470 			"bootm $osaddr; "				\
471 		"fi; "							\
472 	"else; "							\
473 		"echo OS DOWNLOAD FAILED; "				\
474 	"fi;"
475 
476 #define CONFIG_PROG_OS1							\
477 	"$download_cmd $osaddr $osfile; "				\
478 	"if test $? -eq 0; then "					\
479 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
480 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
481 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
482 		"if test $? -ne 0; then "				\
483 			"echo OS PROGRAM FAILED; "			\
484 		"else; "						\
485 			"echo OS PROGRAM SUCCEEDED; "			\
486 		"fi; "							\
487 	"else; "							\
488 		"echo OS DOWNLOAD FAILED; "				\
489 	"fi;"
490 
491 #define CONFIG_PROG_OS2							\
492 	"$download_cmd $osaddr $osfile; "				\
493 	"if test $? -eq 0; then "					\
494 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
495 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
496 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
497 		"if test $? -ne 0; then "				\
498 			"echo OS PROGRAM FAILED; "			\
499 		"else; "						\
500 			"echo OS PROGRAM SUCCEEDED; "			\
501 		"fi; "							\
502 	"else; "							\
503 		"echo OS DOWNLOAD FAILED; "				\
504 	"fi;"
505 
506 #define CONFIG_PROG_FDT1						\
507 	"$download_cmd $fdtaddr $fdtfile; "				\
508 	"if test $? -eq 0; then "					\
509 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
510 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
511 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
512 		"if test $? -ne 0; then "				\
513 			"echo FDT PROGRAM FAILED; "			\
514 		"else; "						\
515 			"echo FDT PROGRAM SUCCEEDED; "			\
516 		"fi; "							\
517 	"else; "							\
518 		"echo FDT DOWNLOAD FAILED; "				\
519 	"fi;"
520 
521 #define CONFIG_PROG_FDT2						\
522 	"$download_cmd $fdtaddr $fdtfile; "				\
523 	"if test $? -eq 0; then "					\
524 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
525 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
526 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
527 		"if test $? -ne 0; then "				\
528 			"echo FDT PROGRAM FAILED; "			\
529 		"else; "						\
530 			"echo FDT PROGRAM SUCCEEDED; "			\
531 		"fi; "							\
532 	"else; "							\
533 		"echo FDT DOWNLOAD FAILED; "				\
534 	"fi;"
535 
536 #define	CONFIG_EXTRA_ENV_SETTINGS					\
537 	"autoload=yes\0"						\
538 	"download_cmd=tftp\0"						\
539 	"console_args=console=ttyS0,115200\0"				\
540 	"root_args=root=/dev/nfs rw\0"					\
541 	"misc_args=ip=on\0"						\
542 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
543 	"bootfile=/home/user/file\0"					\
544 	"osfile=/home/user/board.uImage\0"				\
545 	"fdtfile=/home/user/board.dtb\0"				\
546 	"ubootfile=/home/user/u-boot.bin\0"				\
547 	"fdtaddr=0x1e00000\0"						\
548 	"osaddr=0x1000000\0"						\
549 	"loadaddr=0x1000000\0"						\
550 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
551 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
552 	"prog_os1="CONFIG_PROG_OS1"\0"					\
553 	"prog_os2="CONFIG_PROG_OS2"\0"					\
554 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
555 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
556 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
557 	"bootcmd_flash1=run set_bootargs; "				\
558 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
559 	"bootcmd_flash2=run set_bootargs; "				\
560 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
561 	"bootcmd=run bootcmd_flash1\0"
562 #endif	/* __CONFIG_H */
563