1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite520x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 18 #define CONFIG_SYS_FORM_PMC_XMC 1 19 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 20 21 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 22 #define CONFIG_PCI1 1 /* PCI controller 1 */ 23 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 24 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 26 27 /* 28 * DDR config 29 */ 30 #undef CONFIG_FSL_DDR_INTERACTIVE 31 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 32 #define CONFIG_DDR_SPD 33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 34 #define SPD_EEPROM_ADDRESS 0x54 35 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 36 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 37 #define CONFIG_DDR_ECC 38 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 39 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 40 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 41 #define CONFIG_VERY_BIG_RAM 42 43 #define CONFIG_SYS_CLK_FREQ 66666666 44 45 /* 46 * These can be toggled for performance analysis, otherwise use default. 47 */ 48 #define CONFIG_L2_CACHE /* toggle L2 cache */ 49 #define CONFIG_BTB /* toggle branch predition */ 50 #define CONFIG_ENABLE_36BIT_PHYS 1 51 52 #define CONFIG_SYS_CCSRBAR 0xef000000 53 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 54 55 /* 56 * Diagnostics 57 */ 58 #define CONFIG_SYS_ALT_MEMTEST 59 #define CONFIG_SYS_MEMTEST_START 0x10000000 60 #define CONFIG_SYS_MEMTEST_END 0x20000000 61 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 62 CONFIG_SYS_POST_I2C) 63 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ 64 CONFIG_SYS_I2C_EEPROM_ADDR, \ 65 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 66 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 67 CONFIG_SYS_I2C_RTC_ADDR} 68 69 /* 70 * Memory map 71 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 72 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 73 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 74 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 75 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 76 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 77 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 78 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 79 */ 80 81 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 82 83 /* 84 * NAND flash configuration 85 */ 86 #define CONFIG_SYS_NAND_BASE 0xef800000 87 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 88 #define CONFIG_SYS_MAX_NAND_DEVICE 1 89 #define CONFIG_NAND_ACTL 90 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 91 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 92 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 93 #define CONFIG_SYS_NAND_ACTL_DELAY 25 94 95 /* 96 * NOR flash configuration 97 */ 98 #define CONFIG_SYS_FLASH_BASE 0xfc000000 99 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 100 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 101 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 102 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 103 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 104 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 105 #define CONFIG_FLASH_CFI_DRIVER 106 #define CONFIG_SYS_FLASH_CFI 107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 108 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 109 {0xfbf40000, 0xc0000} } 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 111 112 /* 113 * Chip select configuration 114 */ 115 /* NOR Flash 0 on CS0 */ 116 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 117 BR_PS_16 | \ 118 BR_V) 119 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 120 OR_GPCM_ACS_DIV4 | \ 121 OR_GPCM_SCY_8) 122 123 /* NOR Flash 1 on CS1 */ 124 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 125 BR_PS_16 | \ 126 BR_V) 127 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 128 129 /* NAND flash on CS2 */ 130 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 131 BR_PS_8 | \ 132 BR_V) 133 134 /* NAND flash on CS2 */ 135 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 136 OR_GPCM_BCTLD | \ 137 OR_GPCM_CSNT | \ 138 OR_GPCM_ACS_DIV4 | \ 139 OR_GPCM_SCY_4 | \ 140 OR_GPCM_TRLX | \ 141 OR_GPCM_EHTR) 142 143 /* NAND flash on CS3 */ 144 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 145 BR_PS_8 | \ 146 BR_V) 147 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 148 149 /* 150 * Use L1 as initial stack 151 */ 152 #define CONFIG_SYS_INIT_RAM_LOCK 1 153 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 154 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 155 156 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 158 159 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 160 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 161 162 /* 163 * Serial Port 164 */ 165 #define CONFIG_SYS_NS16550_SERIAL 166 #define CONFIG_SYS_NS16550_REG_SIZE 1 167 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 168 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 169 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 170 #define CONFIG_SYS_BAUDRATE_TABLE \ 171 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 172 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 173 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 174 175 /* 176 * I2C 177 */ 178 #define CONFIG_SYS_I2C 179 #define CONFIG_SYS_I2C_FSL 180 #define CONFIG_SYS_FSL_I2C_SPEED 400000 181 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 182 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 183 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 184 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 185 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 186 187 /* I2C EEPROM */ 188 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 189 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 191 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 192 193 /* I2C RTC */ 194 #define CONFIG_RTC_M41T11 1 195 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 196 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 197 198 /* GPIO */ 199 #define CONFIG_PCA953X 200 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 201 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 202 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 203 204 /* PCA957 @ 0x18 */ 205 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 206 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 207 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 208 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 209 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 210 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 211 #define CONFIG_SYS_PCA953X_MONARCH 0x40 212 #define CONFIG_SYS_PCA953X_EREADY 0x80 213 214 /* PCA957 @ 0x19 */ 215 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 216 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 217 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 218 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 219 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 220 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 221 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 222 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 223 224 /* 12-bit ADC used to measure CPU diode */ 225 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 226 227 /* 228 * General PCI 229 * Memory space is mapped 1-1, but I/O space must start from 0. 230 */ 231 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 232 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 233 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 234 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 235 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 236 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 237 238 /* 239 * Networking options 240 */ 241 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 242 #define CONFIG_MII 1 /* MII PHY management */ 243 #define CONFIG_ETHPRIME "eTSEC1" 244 245 #define CONFIG_TSEC1 1 246 #define CONFIG_TSEC1_NAME "eTSEC1" 247 #define TSEC1_FLAGS TSEC_GIGABIT 248 #define TSEC1_PHY_ADDR 1 249 #define TSEC1_PHYIDX 0 250 #define CONFIG_HAS_ETH0 251 252 #define CONFIG_TSEC2 1 253 #define CONFIG_TSEC2_NAME "eTSEC2" 254 #define TSEC2_FLAGS TSEC_GIGABIT 255 #define TSEC2_PHY_ADDR 2 256 #define TSEC2_PHYIDX 0 257 #define CONFIG_HAS_ETH1 258 259 #define CONFIG_TSEC3 1 260 #define CONFIG_TSEC3_NAME "eTSEC3" 261 #define TSEC3_FLAGS TSEC_GIGABIT 262 #define TSEC3_PHY_ADDR 3 263 #define TSEC3_PHYIDX 0 264 #define CONFIG_HAS_ETH2 265 266 #define CONFIG_TSEC4 1 267 #define CONFIG_TSEC4_NAME "eTSEC4" 268 #define TSEC4_FLAGS TSEC_GIGABIT 269 #define TSEC4_PHY_ADDR 4 270 #define TSEC4_PHYIDX 0 271 #define CONFIG_HAS_ETH3 272 273 /* 274 * BOOTP options 275 */ 276 #define CONFIG_BOOTP_BOOTFILESIZE 277 278 /* 279 * Miscellaneous configurable options 280 */ 281 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 282 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 283 #define CONFIG_PREBOOT /* enable preboot variable */ 284 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 285 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 286 287 /* 288 * For booting Linux, the board info and command line data 289 * have to be in the first 16 MB of memory, since this is 290 * the maximum mapped by the Linux kernel during initialization. 291 */ 292 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 293 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 294 295 /* 296 * Environment Configuration 297 */ 298 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 299 #define CONFIG_ENV_SIZE 0x8000 300 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 301 302 /* 303 * Flash memory map: 304 * fff80000 - ffffffff Pri U-Boot (512 KB) 305 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 306 * fff00000 - fff3ffff Pri FDT (256KB) 307 * fef00000 - ffefffff Pri OS image (16MB) 308 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 309 * 310 * fbf80000 - fbffffff Sec U-Boot (512 KB) 311 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 312 * fbf00000 - fbf3ffff Sec FDT (256KB) 313 * faf00000 - fbefffff Sec OS image (16MB) 314 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 315 */ 316 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 317 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) 318 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 319 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) 320 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 321 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) 322 323 #define CONFIG_PROG_UBOOT1 \ 324 "$download_cmd $loadaddr $ubootfile; " \ 325 "if test $? -eq 0; then " \ 326 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 327 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 328 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 329 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 330 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 331 "if test $? -ne 0; then " \ 332 "echo PROGRAM FAILED; " \ 333 "else; " \ 334 "echo PROGRAM SUCCEEDED; " \ 335 "fi; " \ 336 "else; " \ 337 "echo DOWNLOAD FAILED; " \ 338 "fi;" 339 340 #define CONFIG_PROG_UBOOT2 \ 341 "$download_cmd $loadaddr $ubootfile; " \ 342 "if test $? -eq 0; then " \ 343 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 344 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 345 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 346 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 347 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 348 "if test $? -ne 0; then " \ 349 "echo PROGRAM FAILED; " \ 350 "else; " \ 351 "echo PROGRAM SUCCEEDED; " \ 352 "fi; " \ 353 "else; " \ 354 "echo DOWNLOAD FAILED; " \ 355 "fi;" 356 357 #define CONFIG_BOOT_OS_NET \ 358 "$download_cmd $osaddr $osfile; " \ 359 "if test $? -eq 0; then " \ 360 "if test -n $fdtaddr; then " \ 361 "$download_cmd $fdtaddr $fdtfile; " \ 362 "if test $? -eq 0; then " \ 363 "bootm $osaddr - $fdtaddr; " \ 364 "else; " \ 365 "echo FDT DOWNLOAD FAILED; " \ 366 "fi; " \ 367 "else; " \ 368 "bootm $osaddr; " \ 369 "fi; " \ 370 "else; " \ 371 "echo OS DOWNLOAD FAILED; " \ 372 "fi;" 373 374 #define CONFIG_PROG_OS1 \ 375 "$download_cmd $osaddr $osfile; " \ 376 "if test $? -eq 0; then " \ 377 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 378 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 379 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 380 "if test $? -ne 0; then " \ 381 "echo OS PROGRAM FAILED; " \ 382 "else; " \ 383 "echo OS PROGRAM SUCCEEDED; " \ 384 "fi; " \ 385 "else; " \ 386 "echo OS DOWNLOAD FAILED; " \ 387 "fi;" 388 389 #define CONFIG_PROG_OS2 \ 390 "$download_cmd $osaddr $osfile; " \ 391 "if test $? -eq 0; then " \ 392 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 393 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 394 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 395 "if test $? -ne 0; then " \ 396 "echo OS PROGRAM FAILED; " \ 397 "else; " \ 398 "echo OS PROGRAM SUCCEEDED; " \ 399 "fi; " \ 400 "else; " \ 401 "echo OS DOWNLOAD FAILED; " \ 402 "fi;" 403 404 #define CONFIG_PROG_FDT1 \ 405 "$download_cmd $fdtaddr $fdtfile; " \ 406 "if test $? -eq 0; then " \ 407 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 408 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 409 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 410 "if test $? -ne 0; then " \ 411 "echo FDT PROGRAM FAILED; " \ 412 "else; " \ 413 "echo FDT PROGRAM SUCCEEDED; " \ 414 "fi; " \ 415 "else; " \ 416 "echo FDT DOWNLOAD FAILED; " \ 417 "fi;" 418 419 #define CONFIG_PROG_FDT2 \ 420 "$download_cmd $fdtaddr $fdtfile; " \ 421 "if test $? -eq 0; then " \ 422 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 423 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 424 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 425 "if test $? -ne 0; then " \ 426 "echo FDT PROGRAM FAILED; " \ 427 "else; " \ 428 "echo FDT PROGRAM SUCCEEDED; " \ 429 "fi; " \ 430 "else; " \ 431 "echo FDT DOWNLOAD FAILED; " \ 432 "fi;" 433 434 #define CONFIG_EXTRA_ENV_SETTINGS \ 435 "autoload=yes\0" \ 436 "download_cmd=tftp\0" \ 437 "console_args=console=ttyS0,115200\0" \ 438 "root_args=root=/dev/nfs rw\0" \ 439 "misc_args=ip=on\0" \ 440 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 441 "bootfile=/home/user/file\0" \ 442 "osfile=/home/user/board.uImage\0" \ 443 "fdtfile=/home/user/board.dtb\0" \ 444 "ubootfile=/home/user/u-boot.bin\0" \ 445 "fdtaddr=0x1e00000\0" \ 446 "osaddr=0x1000000\0" \ 447 "loadaddr=0x1000000\0" \ 448 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 449 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 450 "prog_os1="CONFIG_PROG_OS1"\0" \ 451 "prog_os2="CONFIG_PROG_OS2"\0" \ 452 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 453 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 454 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 455 "bootcmd_flash1=run set_bootargs; " \ 456 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 457 "bootcmd_flash2=run set_bootargs; " \ 458 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 459 "bootcmd=run bootcmd_flash1\0" 460 #endif /* __CONFIG_H */ 461