1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2008 Extreme Engineering Solutions, Inc. 4 * Copyright 2004-2008 Freescale Semiconductor, Inc. 5 */ 6 7 /* 8 * xpedite520x board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 17 #define CONFIG_SYS_FORM_PMC_XMC 1 18 19 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 20 #define CONFIG_PCI1 1 /* PCI controller 1 */ 21 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 23 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 24 25 /* 26 * DDR config 27 */ 28 #undef CONFIG_FSL_DDR_INTERACTIVE 29 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 30 #define CONFIG_DDR_SPD 31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 32 #define SPD_EEPROM_ADDRESS 0x54 33 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 35 #define CONFIG_DDR_ECC 36 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 37 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 39 #define CONFIG_VERY_BIG_RAM 40 41 #define CONFIG_SYS_CLK_FREQ 66666666 42 43 /* 44 * These can be toggled for performance analysis, otherwise use default. 45 */ 46 #define CONFIG_L2_CACHE /* toggle L2 cache */ 47 #define CONFIG_BTB /* toggle branch predition */ 48 #define CONFIG_ENABLE_36BIT_PHYS 1 49 50 #define CONFIG_SYS_CCSRBAR 0xef000000 51 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 52 53 /* 54 * Diagnostics 55 */ 56 #define CONFIG_SYS_MEMTEST_START 0x10000000 57 #define CONFIG_SYS_MEMTEST_END 0x20000000 58 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 59 CONFIG_SYS_POST_I2C) 60 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ 61 CONFIG_SYS_I2C_EEPROM_ADDR, \ 62 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 63 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 64 CONFIG_SYS_I2C_RTC_ADDR} 65 66 /* 67 * Memory map 68 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 69 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 70 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 71 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 72 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 73 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 74 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 75 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 76 */ 77 78 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 79 80 /* 81 * NAND flash configuration 82 */ 83 #define CONFIG_SYS_NAND_BASE 0xef800000 84 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 85 #define CONFIG_SYS_MAX_NAND_DEVICE 1 86 #define CONFIG_NAND_ACTL 87 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 88 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 89 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 90 #define CONFIG_SYS_NAND_ACTL_DELAY 25 91 92 /* 93 * NOR flash configuration 94 */ 95 #define CONFIG_SYS_FLASH_BASE 0xfc000000 96 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 97 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 98 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 99 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 100 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 101 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 102 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 103 {0xfbf40000, 0xc0000} } 104 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 105 106 /* 107 * Chip select configuration 108 */ 109 /* NOR Flash 0 on CS0 */ 110 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 111 BR_PS_16 | \ 112 BR_V) 113 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 114 OR_GPCM_ACS_DIV4 | \ 115 OR_GPCM_SCY_8) 116 117 /* NOR Flash 1 on CS1 */ 118 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 119 BR_PS_16 | \ 120 BR_V) 121 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 122 123 /* NAND flash on CS2 */ 124 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 125 BR_PS_8 | \ 126 BR_V) 127 128 /* NAND flash on CS2 */ 129 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 130 OR_GPCM_BCTLD | \ 131 OR_GPCM_CSNT | \ 132 OR_GPCM_ACS_DIV4 | \ 133 OR_GPCM_SCY_4 | \ 134 OR_GPCM_TRLX | \ 135 OR_GPCM_EHTR) 136 137 /* NAND flash on CS3 */ 138 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 139 BR_PS_8 | \ 140 BR_V) 141 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 142 143 /* 144 * Use L1 as initial stack 145 */ 146 #define CONFIG_SYS_INIT_RAM_LOCK 1 147 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 148 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 149 150 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 151 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 152 153 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 154 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 155 156 /* 157 * Serial Port 158 */ 159 #define CONFIG_SYS_NS16550_SERIAL 160 #define CONFIG_SYS_NS16550_REG_SIZE 1 161 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 162 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 163 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 164 #define CONFIG_SYS_BAUDRATE_TABLE \ 165 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 166 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 167 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 168 169 /* 170 * I2C 171 */ 172 #define CONFIG_SYS_I2C 173 #define CONFIG_SYS_I2C_FSL 174 #define CONFIG_SYS_FSL_I2C_SPEED 400000 175 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 176 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 177 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 178 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 179 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 180 181 /* I2C EEPROM */ 182 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 183 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 184 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 185 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 186 187 /* I2C RTC */ 188 #define CONFIG_RTC_M41T11 1 189 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 190 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 191 192 /* GPIO */ 193 #define CONFIG_PCA953X 194 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 195 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 196 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 197 198 /* PCA957 @ 0x18 */ 199 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 200 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 201 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 202 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 203 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 204 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 205 #define CONFIG_SYS_PCA953X_MONARCH 0x40 206 #define CONFIG_SYS_PCA953X_EREADY 0x80 207 208 /* PCA957 @ 0x19 */ 209 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 210 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 211 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 212 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 213 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 214 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 215 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 216 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 217 218 /* 12-bit ADC used to measure CPU diode */ 219 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 220 221 /* 222 * General PCI 223 * Memory space is mapped 1-1, but I/O space must start from 0. 224 */ 225 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 226 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 227 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 228 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 229 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 230 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 231 232 /* 233 * Networking options 234 */ 235 #define CONFIG_ETHPRIME "eTSEC1" 236 237 #define CONFIG_TSEC1 1 238 #define CONFIG_TSEC1_NAME "eTSEC1" 239 #define TSEC1_FLAGS TSEC_GIGABIT 240 #define TSEC1_PHY_ADDR 1 241 #define TSEC1_PHYIDX 0 242 #define CONFIG_HAS_ETH0 243 244 #define CONFIG_TSEC2 1 245 #define CONFIG_TSEC2_NAME "eTSEC2" 246 #define TSEC2_FLAGS TSEC_GIGABIT 247 #define TSEC2_PHY_ADDR 2 248 #define TSEC2_PHYIDX 0 249 #define CONFIG_HAS_ETH1 250 251 #define CONFIG_TSEC3 1 252 #define CONFIG_TSEC3_NAME "eTSEC3" 253 #define TSEC3_FLAGS TSEC_GIGABIT 254 #define TSEC3_PHY_ADDR 3 255 #define TSEC3_PHYIDX 0 256 #define CONFIG_HAS_ETH2 257 258 #define CONFIG_TSEC4 1 259 #define CONFIG_TSEC4_NAME "eTSEC4" 260 #define TSEC4_FLAGS TSEC_GIGABIT 261 #define TSEC4_PHY_ADDR 4 262 #define TSEC4_PHYIDX 0 263 #define CONFIG_HAS_ETH3 264 265 /* 266 * BOOTP options 267 */ 268 #define CONFIG_BOOTP_BOOTFILESIZE 269 270 /* 271 * Miscellaneous configurable options 272 */ 273 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 274 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 275 #define CONFIG_PREBOOT /* enable preboot variable */ 276 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 277 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 278 279 /* 280 * For booting Linux, the board info and command line data 281 * have to be in the first 16 MB of memory, since this is 282 * the maximum mapped by the Linux kernel during initialization. 283 */ 284 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 285 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 286 287 /* 288 * Environment Configuration 289 */ 290 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 291 #define CONFIG_ENV_SIZE 0x8000 292 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 293 294 /* 295 * Flash memory map: 296 * fff80000 - ffffffff Pri U-Boot (512 KB) 297 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 298 * fff00000 - fff3ffff Pri FDT (256KB) 299 * fef00000 - ffefffff Pri OS image (16MB) 300 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 301 * 302 * fbf80000 - fbffffff Sec U-Boot (512 KB) 303 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 304 * fbf00000 - fbf3ffff Sec FDT (256KB) 305 * faf00000 - fbefffff Sec OS image (16MB) 306 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 307 */ 308 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 309 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) 310 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 311 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) 312 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 313 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) 314 315 #define CONFIG_PROG_UBOOT1 \ 316 "$download_cmd $loadaddr $ubootfile; " \ 317 "if test $? -eq 0; then " \ 318 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 319 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 320 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 321 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 322 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 323 "if test $? -ne 0; then " \ 324 "echo PROGRAM FAILED; " \ 325 "else; " \ 326 "echo PROGRAM SUCCEEDED; " \ 327 "fi; " \ 328 "else; " \ 329 "echo DOWNLOAD FAILED; " \ 330 "fi;" 331 332 #define CONFIG_PROG_UBOOT2 \ 333 "$download_cmd $loadaddr $ubootfile; " \ 334 "if test $? -eq 0; then " \ 335 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 336 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 337 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 338 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 339 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 340 "if test $? -ne 0; then " \ 341 "echo PROGRAM FAILED; " \ 342 "else; " \ 343 "echo PROGRAM SUCCEEDED; " \ 344 "fi; " \ 345 "else; " \ 346 "echo DOWNLOAD FAILED; " \ 347 "fi;" 348 349 #define CONFIG_BOOT_OS_NET \ 350 "$download_cmd $osaddr $osfile; " \ 351 "if test $? -eq 0; then " \ 352 "if test -n $fdtaddr; then " \ 353 "$download_cmd $fdtaddr $fdtfile; " \ 354 "if test $? -eq 0; then " \ 355 "bootm $osaddr - $fdtaddr; " \ 356 "else; " \ 357 "echo FDT DOWNLOAD FAILED; " \ 358 "fi; " \ 359 "else; " \ 360 "bootm $osaddr; " \ 361 "fi; " \ 362 "else; " \ 363 "echo OS DOWNLOAD FAILED; " \ 364 "fi;" 365 366 #define CONFIG_PROG_OS1 \ 367 "$download_cmd $osaddr $osfile; " \ 368 "if test $? -eq 0; then " \ 369 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 370 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 371 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 372 "if test $? -ne 0; then " \ 373 "echo OS PROGRAM FAILED; " \ 374 "else; " \ 375 "echo OS PROGRAM SUCCEEDED; " \ 376 "fi; " \ 377 "else; " \ 378 "echo OS DOWNLOAD FAILED; " \ 379 "fi;" 380 381 #define CONFIG_PROG_OS2 \ 382 "$download_cmd $osaddr $osfile; " \ 383 "if test $? -eq 0; then " \ 384 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 385 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 386 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 387 "if test $? -ne 0; then " \ 388 "echo OS PROGRAM FAILED; " \ 389 "else; " \ 390 "echo OS PROGRAM SUCCEEDED; " \ 391 "fi; " \ 392 "else; " \ 393 "echo OS DOWNLOAD FAILED; " \ 394 "fi;" 395 396 #define CONFIG_PROG_FDT1 \ 397 "$download_cmd $fdtaddr $fdtfile; " \ 398 "if test $? -eq 0; then " \ 399 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 400 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 401 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 402 "if test $? -ne 0; then " \ 403 "echo FDT PROGRAM FAILED; " \ 404 "else; " \ 405 "echo FDT PROGRAM SUCCEEDED; " \ 406 "fi; " \ 407 "else; " \ 408 "echo FDT DOWNLOAD FAILED; " \ 409 "fi;" 410 411 #define CONFIG_PROG_FDT2 \ 412 "$download_cmd $fdtaddr $fdtfile; " \ 413 "if test $? -eq 0; then " \ 414 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 415 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 416 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 417 "if test $? -ne 0; then " \ 418 "echo FDT PROGRAM FAILED; " \ 419 "else; " \ 420 "echo FDT PROGRAM SUCCEEDED; " \ 421 "fi; " \ 422 "else; " \ 423 "echo FDT DOWNLOAD FAILED; " \ 424 "fi;" 425 426 #define CONFIG_EXTRA_ENV_SETTINGS \ 427 "autoload=yes\0" \ 428 "download_cmd=tftp\0" \ 429 "console_args=console=ttyS0,115200\0" \ 430 "root_args=root=/dev/nfs rw\0" \ 431 "misc_args=ip=on\0" \ 432 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 433 "bootfile=/home/user/file\0" \ 434 "osfile=/home/user/board.uImage\0" \ 435 "fdtfile=/home/user/board.dtb\0" \ 436 "ubootfile=/home/user/u-boot.bin\0" \ 437 "fdtaddr=0x1e00000\0" \ 438 "osaddr=0x1000000\0" \ 439 "loadaddr=0x1000000\0" \ 440 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 441 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 442 "prog_os1="CONFIG_PROG_OS1"\0" \ 443 "prog_os2="CONFIG_PROG_OS2"\0" \ 444 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 445 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 446 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 447 "bootcmd_flash1=run set_bootargs; " \ 448 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 449 "bootcmd_flash2=run set_bootargs; " \ 450 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 451 "bootcmd=run bootcmd_flash1\0" 452 #endif /* __CONFIG_H */ 453