1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite520x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_XPEDITE5200 1 18 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 19 #define CONFIG_SYS_FORM_PMC_XMC 1 20 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 21 22 #ifndef CONFIG_SYS_TEXT_BASE 23 #define CONFIG_SYS_TEXT_BASE 0xfff80000 24 #endif 25 26 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 27 #define CONFIG_PCI1 1 /* PCI controller 1 */ 28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 31 32 /* 33 * DDR config 34 */ 35 #undef CONFIG_FSL_DDR_INTERACTIVE 36 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 37 #define CONFIG_DDR_SPD 38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 39 #define SPD_EEPROM_ADDRESS 0x54 40 #define CONFIG_NUM_DDR_CONTROLLERS 1 41 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 42 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 43 #define CONFIG_DDR_ECC 44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 46 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 47 #define CONFIG_VERY_BIG_RAM 48 49 #define CONFIG_SYS_CLK_FREQ 66666666 50 51 /* 52 * These can be toggled for performance analysis, otherwise use default. 53 */ 54 #define CONFIG_L2_CACHE /* toggle L2 cache */ 55 #define CONFIG_BTB /* toggle branch predition */ 56 #define CONFIG_ENABLE_36BIT_PHYS 1 57 58 #define CONFIG_SYS_CCSRBAR 0xef000000 59 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 60 61 /* 62 * Diagnostics 63 */ 64 #define CONFIG_SYS_ALT_MEMTEST 65 #define CONFIG_SYS_MEMTEST_START 0x10000000 66 #define CONFIG_SYS_MEMTEST_END 0x20000000 67 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 68 CONFIG_SYS_POST_I2C) 69 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ 70 CONFIG_SYS_I2C_EEPROM_ADDR, \ 71 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 72 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 73 CONFIG_SYS_I2C_RTC_ADDR} 74 75 /* 76 * Memory map 77 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 78 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 79 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 80 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 81 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 82 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 83 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 84 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 85 */ 86 87 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 88 89 /* 90 * NAND flash configuration 91 */ 92 #define CONFIG_SYS_NAND_BASE 0xef800000 93 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 94 #define CONFIG_SYS_MAX_NAND_DEVICE 1 95 #define CONFIG_NAND_ACTL 96 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 97 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 98 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 99 #define CONFIG_SYS_NAND_ACTL_DELAY 25 100 101 /* 102 * NOR flash configuration 103 */ 104 #define CONFIG_SYS_FLASH_BASE 0xfc000000 105 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 106 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 107 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 108 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 109 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 110 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 111 #define CONFIG_FLASH_CFI_DRIVER 112 #define CONFIG_SYS_FLASH_CFI 113 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 114 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 115 {0xfbf40000, 0xc0000} } 116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 117 118 /* 119 * Chip select configuration 120 */ 121 /* NOR Flash 0 on CS0 */ 122 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 123 BR_PS_16 | \ 124 BR_V) 125 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 126 OR_GPCM_ACS_DIV4 | \ 127 OR_GPCM_SCY_8) 128 129 /* NOR Flash 1 on CS1 */ 130 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 131 BR_PS_16 | \ 132 BR_V) 133 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 134 135 /* NAND flash on CS2 */ 136 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 137 BR_PS_8 | \ 138 BR_V) 139 140 /* NAND flash on CS2 */ 141 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 142 OR_GPCM_BCTLD | \ 143 OR_GPCM_CSNT | \ 144 OR_GPCM_ACS_DIV4 | \ 145 OR_GPCM_SCY_4 | \ 146 OR_GPCM_TRLX | \ 147 OR_GPCM_EHTR) 148 149 /* NAND flash on CS3 */ 150 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 151 BR_PS_8 | \ 152 BR_V) 153 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 154 155 /* 156 * Use L1 as initial stack 157 */ 158 #define CONFIG_SYS_INIT_RAM_LOCK 1 159 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 160 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 161 162 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 163 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 164 165 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 166 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 167 168 /* 169 * Serial Port 170 */ 171 #define CONFIG_CONS_INDEX 1 172 #define CONFIG_SYS_NS16550_SERIAL 173 #define CONFIG_SYS_NS16550_REG_SIZE 1 174 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 175 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 176 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 177 #define CONFIG_SYS_BAUDRATE_TABLE \ 178 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 179 #define CONFIG_BAUDRATE 115200 180 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 181 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 182 183 /* 184 * I2C 185 */ 186 #define CONFIG_SYS_I2C 187 #define CONFIG_SYS_I2C_FSL 188 #define CONFIG_SYS_FSL_I2C_SPEED 400000 189 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 190 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 191 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 192 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 193 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 194 195 /* I2C EEPROM */ 196 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 197 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 198 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 199 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 200 201 /* I2C RTC */ 202 #define CONFIG_RTC_M41T11 1 203 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 204 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 205 206 /* GPIO */ 207 #define CONFIG_PCA953X 208 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 209 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 210 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 211 212 /* PCA957 @ 0x18 */ 213 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 214 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 215 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 216 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 217 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 218 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 219 #define CONFIG_SYS_PCA953X_MONARCH 0x40 220 #define CONFIG_SYS_PCA953X_EREADY 0x80 221 222 /* PCA957 @ 0x19 */ 223 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 224 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 225 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 226 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 227 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 228 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 229 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 230 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 231 232 /* 12-bit ADC used to measure CPU diode */ 233 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 234 235 /* 236 * General PCI 237 * Memory space is mapped 1-1, but I/O space must start from 0. 238 */ 239 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 240 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 241 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 242 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 243 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 244 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 245 246 /* 247 * Networking options 248 */ 249 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 250 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 251 #define CONFIG_MII 1 /* MII PHY management */ 252 #define CONFIG_ETHPRIME "eTSEC1" 253 254 #define CONFIG_TSEC1 1 255 #define CONFIG_TSEC1_NAME "eTSEC1" 256 #define TSEC1_FLAGS TSEC_GIGABIT 257 #define TSEC1_PHY_ADDR 1 258 #define TSEC1_PHYIDX 0 259 #define CONFIG_HAS_ETH0 260 261 #define CONFIG_TSEC2 1 262 #define CONFIG_TSEC2_NAME "eTSEC2" 263 #define TSEC2_FLAGS TSEC_GIGABIT 264 #define TSEC2_PHY_ADDR 2 265 #define TSEC2_PHYIDX 0 266 #define CONFIG_HAS_ETH1 267 268 #define CONFIG_TSEC3 1 269 #define CONFIG_TSEC3_NAME "eTSEC3" 270 #define TSEC3_FLAGS TSEC_GIGABIT 271 #define TSEC3_PHY_ADDR 3 272 #define TSEC3_PHYIDX 0 273 #define CONFIG_HAS_ETH2 274 275 #define CONFIG_TSEC4 1 276 #define CONFIG_TSEC4_NAME "eTSEC4" 277 #define TSEC4_FLAGS TSEC_GIGABIT 278 #define TSEC4_PHY_ADDR 4 279 #define TSEC4_PHYIDX 0 280 #define CONFIG_HAS_ETH3 281 282 /* 283 * BOOTP options 284 */ 285 #define CONFIG_BOOTP_BOOTFILESIZE 286 #define CONFIG_BOOTP_BOOTPATH 287 #define CONFIG_BOOTP_GATEWAY 288 289 /* 290 * Command configuration. 291 */ 292 #define CONFIG_CMD_DATE 293 #define CONFIG_CMD_EEPROM 294 #define CONFIG_CMD_JFFS2 295 #define CONFIG_CMD_NAND 296 #define CONFIG_CMD_PCA953X 297 #define CONFIG_CMD_PCA953X_INFO 298 #define CONFIG_CMD_PCI 299 #define CONFIG_CMD_PCI_ENUM 300 #define CONFIG_CMD_REGINFO 301 302 /* 303 * Miscellaneous configurable options 304 */ 305 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 306 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 307 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 308 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 309 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 310 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 311 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 312 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 313 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 314 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 315 #define CONFIG_PREBOOT /* enable preboot variable */ 316 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 317 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 318 319 /* 320 * For booting Linux, the board info and command line data 321 * have to be in the first 16 MB of memory, since this is 322 * the maximum mapped by the Linux kernel during initialization. 323 */ 324 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 325 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 326 327 /* 328 * Environment Configuration 329 */ 330 #define CONFIG_ENV_IS_IN_FLASH 1 331 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 332 #define CONFIG_ENV_SIZE 0x8000 333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 334 335 /* 336 * Flash memory map: 337 * fff80000 - ffffffff Pri U-Boot (512 KB) 338 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 339 * fff00000 - fff3ffff Pri FDT (256KB) 340 * fef00000 - ffefffff Pri OS image (16MB) 341 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 342 * 343 * fbf80000 - fbffffff Sec U-Boot (512 KB) 344 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 345 * fbf00000 - fbf3ffff Sec FDT (256KB) 346 * faf00000 - fbefffff Sec OS image (16MB) 347 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 348 */ 349 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 350 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) 351 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 352 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) 353 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 354 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) 355 356 #define CONFIG_PROG_UBOOT1 \ 357 "$download_cmd $loadaddr $ubootfile; " \ 358 "if test $? -eq 0; then " \ 359 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 360 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 361 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 362 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 363 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 364 "if test $? -ne 0; then " \ 365 "echo PROGRAM FAILED; " \ 366 "else; " \ 367 "echo PROGRAM SUCCEEDED; " \ 368 "fi; " \ 369 "else; " \ 370 "echo DOWNLOAD FAILED; " \ 371 "fi;" 372 373 #define CONFIG_PROG_UBOOT2 \ 374 "$download_cmd $loadaddr $ubootfile; " \ 375 "if test $? -eq 0; then " \ 376 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 377 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 378 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 379 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 380 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 381 "if test $? -ne 0; then " \ 382 "echo PROGRAM FAILED; " \ 383 "else; " \ 384 "echo PROGRAM SUCCEEDED; " \ 385 "fi; " \ 386 "else; " \ 387 "echo DOWNLOAD FAILED; " \ 388 "fi;" 389 390 #define CONFIG_BOOT_OS_NET \ 391 "$download_cmd $osaddr $osfile; " \ 392 "if test $? -eq 0; then " \ 393 "if test -n $fdtaddr; then " \ 394 "$download_cmd $fdtaddr $fdtfile; " \ 395 "if test $? -eq 0; then " \ 396 "bootm $osaddr - $fdtaddr; " \ 397 "else; " \ 398 "echo FDT DOWNLOAD FAILED; " \ 399 "fi; " \ 400 "else; " \ 401 "bootm $osaddr; " \ 402 "fi; " \ 403 "else; " \ 404 "echo OS DOWNLOAD FAILED; " \ 405 "fi;" 406 407 #define CONFIG_PROG_OS1 \ 408 "$download_cmd $osaddr $osfile; " \ 409 "if test $? -eq 0; then " \ 410 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 411 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 412 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 413 "if test $? -ne 0; then " \ 414 "echo OS PROGRAM FAILED; " \ 415 "else; " \ 416 "echo OS PROGRAM SUCCEEDED; " \ 417 "fi; " \ 418 "else; " \ 419 "echo OS DOWNLOAD FAILED; " \ 420 "fi;" 421 422 #define CONFIG_PROG_OS2 \ 423 "$download_cmd $osaddr $osfile; " \ 424 "if test $? -eq 0; then " \ 425 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 426 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 427 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 428 "if test $? -ne 0; then " \ 429 "echo OS PROGRAM FAILED; " \ 430 "else; " \ 431 "echo OS PROGRAM SUCCEEDED; " \ 432 "fi; " \ 433 "else; " \ 434 "echo OS DOWNLOAD FAILED; " \ 435 "fi;" 436 437 #define CONFIG_PROG_FDT1 \ 438 "$download_cmd $fdtaddr $fdtfile; " \ 439 "if test $? -eq 0; then " \ 440 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 441 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 442 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 443 "if test $? -ne 0; then " \ 444 "echo FDT PROGRAM FAILED; " \ 445 "else; " \ 446 "echo FDT PROGRAM SUCCEEDED; " \ 447 "fi; " \ 448 "else; " \ 449 "echo FDT DOWNLOAD FAILED; " \ 450 "fi;" 451 452 #define CONFIG_PROG_FDT2 \ 453 "$download_cmd $fdtaddr $fdtfile; " \ 454 "if test $? -eq 0; then " \ 455 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 456 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 457 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 458 "if test $? -ne 0; then " \ 459 "echo FDT PROGRAM FAILED; " \ 460 "else; " \ 461 "echo FDT PROGRAM SUCCEEDED; " \ 462 "fi; " \ 463 "else; " \ 464 "echo FDT DOWNLOAD FAILED; " \ 465 "fi;" 466 467 #define CONFIG_EXTRA_ENV_SETTINGS \ 468 "autoload=yes\0" \ 469 "download_cmd=tftp\0" \ 470 "console_args=console=ttyS0,115200\0" \ 471 "root_args=root=/dev/nfs rw\0" \ 472 "misc_args=ip=on\0" \ 473 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 474 "bootfile=/home/user/file\0" \ 475 "osfile=/home/user/board.uImage\0" \ 476 "fdtfile=/home/user/board.dtb\0" \ 477 "ubootfile=/home/user/u-boot.bin\0" \ 478 "fdtaddr=0x1e00000\0" \ 479 "osaddr=0x1000000\0" \ 480 "loadaddr=0x1000000\0" \ 481 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 482 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 483 "prog_os1="CONFIG_PROG_OS1"\0" \ 484 "prog_os2="CONFIG_PROG_OS2"\0" \ 485 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 486 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 487 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 488 "bootcmd_flash1=run set_bootargs; " \ 489 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 490 "bootcmd_flash2=run set_bootargs; " \ 491 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 492 "bootcmd=run bootcmd_flash1\0" 493 #endif /* __CONFIG_H */ 494