1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * xpedite520x board configuration file 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* 31 * High Level Configuration Options 32 */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 37 #define CONFIG_XPEDITE5200 1 38 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 39 #define CONFIG_SYS_FORM_PMC_XMC 1 40 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 41 42 #ifndef CONFIG_SYS_TEXT_BASE 43 #define CONFIG_SYS_TEXT_BASE 0xfff80000 44 #endif 45 46 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 47 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ 48 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 49 #define CONFIG_PCI1 1 /* PCI controller 1 */ 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 53 54 /* 55 * DDR config 56 */ 57 #define CONFIG_FSL_DDR2 58 #undef CONFIG_FSL_DDR_INTERACTIVE 59 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 60 #define CONFIG_DDR_SPD 61 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 62 #define SPD_EEPROM_ADDRESS 0x54 63 #define CONFIG_NUM_DDR_CONTROLLERS 1 64 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 65 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 66 #define CONFIG_DDR_ECC 67 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 68 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 69 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 70 #define CONFIG_VERY_BIG_RAM 71 72 #define CONFIG_SYS_CLK_FREQ 66666666 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE /* toggle L2 cache */ 78 #define CONFIG_BTB /* toggle branch predition */ 79 #define CONFIG_ENABLE_36BIT_PHYS 1 80 81 #define CONFIG_SYS_CCSRBAR 0xef000000 82 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 83 84 /* 85 * Diagnostics 86 */ 87 #define CONFIG_SYS_ALT_MEMTEST 88 #define CONFIG_SYS_MEMTEST_START 0x10000000 89 #define CONFIG_SYS_MEMTEST_END 0x20000000 90 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 91 CONFIG_SYS_POST_I2C) 92 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ 93 CONFIG_SYS_I2C_EEPROM_ADDR, \ 94 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 95 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 96 CONFIG_SYS_I2C_RTC_ADDR} 97 98 /* 99 * Memory map 100 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 101 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 102 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 103 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 104 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 105 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 106 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 107 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 108 */ 109 110 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 111 112 /* 113 * NAND flash configuration 114 */ 115 #define CONFIG_SYS_NAND_BASE 0xef800000 116 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 117 #define CONFIG_SYS_MAX_NAND_DEVICE 1 118 #define CONFIG_NAND_ACTL 119 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 120 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 121 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 122 #define CONFIG_SYS_NAND_ACTL_DELAY 25 123 124 /* 125 * NOR flash configuration 126 */ 127 #define CONFIG_SYS_FLASH_BASE 0xfc000000 128 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 129 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 130 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 131 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 132 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 133 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 134 #define CONFIG_FLASH_CFI_DRIVER 135 #define CONFIG_SYS_FLASH_CFI 136 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 137 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 138 {0xfbf40000, 0xc0000} } 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 140 141 /* 142 * Chip select configuration 143 */ 144 /* NOR Flash 0 on CS0 */ 145 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 146 BR_PS_16 | \ 147 BR_V) 148 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 149 OR_GPCM_ACS_DIV4 | \ 150 OR_GPCM_SCY_8) 151 152 /* NOR Flash 1 on CS1 */ 153 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 154 BR_PS_16 | \ 155 BR_V) 156 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 157 158 /* NAND flash on CS2 */ 159 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 160 BR_PS_8 | \ 161 BR_V) 162 163 /* NAND flash on CS2 */ 164 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 165 OR_GPCM_BCTLD | \ 166 OR_GPCM_CSNT | \ 167 OR_GPCM_ACS_DIV4 | \ 168 OR_GPCM_SCY_4 | \ 169 OR_GPCM_TRLX | \ 170 OR_GPCM_EHTR) 171 172 /* NAND flash on CS3 */ 173 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 174 BR_PS_8 | \ 175 BR_V) 176 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 177 178 /* 179 * Use L1 as initial stack 180 */ 181 #define CONFIG_SYS_INIT_RAM_LOCK 1 182 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 183 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 184 185 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 186 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 187 188 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 189 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 190 191 /* 192 * Serial Port 193 */ 194 #define CONFIG_CONS_INDEX 1 195 #define CONFIG_SYS_NS16550 196 #define CONFIG_SYS_NS16550_SERIAL 197 #define CONFIG_SYS_NS16550_REG_SIZE 1 198 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 201 #define CONFIG_SYS_BAUDRATE_TABLE \ 202 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 203 #define CONFIG_BAUDRATE 115200 204 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 205 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 206 207 /* 208 * Use the HUSH parser 209 */ 210 #define CONFIG_SYS_HUSH_PARSER 211 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 212 213 /* 214 * Pass open firmware flat tree 215 */ 216 #define CONFIG_OF_LIBFDT 1 217 #define CONFIG_OF_BOARD_SETUP 1 218 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 219 220 /* 221 * I2C 222 */ 223 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 224 #define CONFIG_HARD_I2C /* I2C with hardware support */ 225 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 226 #define CONFIG_SYS_I2C_SLAVE 0x7F 227 #define CONFIG_SYS_I2C_OFFSET 0x3000 228 #define CONFIG_SYS_I2C2_OFFSET 0x3100 229 #define CONFIG_I2C_MULTI_BUS 230 231 /* I2C EEPROM */ 232 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 233 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 236 237 /* I2C RTC */ 238 #define CONFIG_RTC_M41T11 1 239 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 240 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 241 242 /* GPIO */ 243 #define CONFIG_PCA953X 244 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 245 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 246 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 247 248 /* PCA957 @ 0x18 */ 249 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 250 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 251 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 252 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 253 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 254 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 255 #define CONFIG_SYS_PCA953X_MONARCH 0x40 256 #define CONFIG_SYS_PCA953X_EREADY 0x80 257 258 /* PCA957 @ 0x19 */ 259 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 260 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 261 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 262 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 263 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 264 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 265 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 266 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 267 268 /* 12-bit ADC used to measure CPU diode */ 269 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 270 271 /* 272 * General PCI 273 * Memory space is mapped 1-1, but I/O space must start from 0. 274 */ 275 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 276 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 277 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 278 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 279 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 280 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 281 282 /* 283 * Networking options 284 */ 285 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 286 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 287 #define CONFIG_NET_MULTI 1 288 #define CONFIG_MII 1 /* MII PHY management */ 289 #define CONFIG_ETHPRIME "eTSEC1" 290 291 #define CONFIG_TSEC1 1 292 #define CONFIG_TSEC1_NAME "eTSEC1" 293 #define TSEC1_FLAGS TSEC_GIGABIT 294 #define TSEC1_PHY_ADDR 1 295 #define TSEC1_PHYIDX 0 296 #define CONFIG_HAS_ETH0 297 298 #define CONFIG_TSEC2 1 299 #define CONFIG_TSEC2_NAME "eTSEC2" 300 #define TSEC2_FLAGS TSEC_GIGABIT 301 #define TSEC2_PHY_ADDR 2 302 #define TSEC2_PHYIDX 0 303 #define CONFIG_HAS_ETH1 304 305 #define CONFIG_TSEC3 1 306 #define CONFIG_TSEC3_NAME "eTSEC3" 307 #define TSEC3_FLAGS TSEC_GIGABIT 308 #define TSEC3_PHY_ADDR 3 309 #define TSEC3_PHYIDX 0 310 #define CONFIG_HAS_ETH2 311 312 #define CONFIG_TSEC4 1 313 #define CONFIG_TSEC4_NAME "eTSEC4" 314 #define TSEC4_FLAGS TSEC_GIGABIT 315 #define TSEC4_PHY_ADDR 4 316 #define TSEC4_PHYIDX 0 317 #define CONFIG_HAS_ETH3 318 319 /* 320 * BOOTP options 321 */ 322 #define CONFIG_BOOTP_BOOTFILESIZE 323 #define CONFIG_BOOTP_BOOTPATH 324 #define CONFIG_BOOTP_GATEWAY 325 326 /* 327 * Command configuration. 328 */ 329 #include <config_cmd_default.h> 330 331 #define CONFIG_CMD_ASKENV 332 #define CONFIG_CMD_DATE 333 #define CONFIG_CMD_DHCP 334 #define CONFIG_CMD_EEPROM 335 #define CONFIG_CMD_ELF 336 #define CONFIG_CMD_SAVEENV 337 #define CONFIG_CMD_FLASH 338 #define CONFIG_CMD_I2C 339 #define CONFIG_CMD_JFFS2 340 #define CONFIG_CMD_MII 341 #define CONFIG_CMD_NAND 342 #define CONFIG_CMD_NET 343 #define CONFIG_CMD_PCA953X 344 #define CONFIG_CMD_PCA953X_INFO 345 #define CONFIG_CMD_PCI 346 #define CONFIG_CMD_PCI_ENUM 347 #define CONFIG_CMD_PING 348 #define CONFIG_CMD_SNTP 349 #define CONFIG_CMD_REGINFO 350 351 /* 352 * Miscellaneous configurable options 353 */ 354 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 355 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 356 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 357 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 358 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 359 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 360 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 361 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 362 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 363 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 364 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 365 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ 366 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 367 #define CONFIG_PREBOOT /* enable preboot variable */ 368 #define CONFIG_FIT 1 369 #define CONFIG_FIT_VERBOSE 1 370 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 371 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 372 373 /* 374 * For booting Linux, the board info and command line data 375 * have to be in the first 16 MB of memory, since this is 376 * the maximum mapped by the Linux kernel during initialization. 377 */ 378 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 379 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 380 381 /* 382 * Environment Configuration 383 */ 384 #define CONFIG_ENV_IS_IN_FLASH 1 385 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 386 #define CONFIG_ENV_SIZE 0x8000 387 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 388 389 /* 390 * Flash memory map: 391 * fff80000 - ffffffff Pri U-Boot (512 KB) 392 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 393 * fff00000 - fff3ffff Pri FDT (256KB) 394 * fef00000 - ffefffff Pri OS image (16MB) 395 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 396 * 397 * fbf80000 - fbffffff Sec U-Boot (512 KB) 398 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 399 * fbf00000 - fbf3ffff Sec FDT (256KB) 400 * faf00000 - fbefffff Sec OS image (16MB) 401 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 402 */ 403 #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) 404 #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000) 405 #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) 406 #define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000) 407 #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) 408 #define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000) 409 410 #define CONFIG_PROG_UBOOT1 \ 411 "$download_cmd $loadaddr $ubootfile; " \ 412 "if test $? -eq 0; then " \ 413 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 414 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 415 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 416 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 417 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 418 "if test $? -ne 0; then " \ 419 "echo PROGRAM FAILED; " \ 420 "else; " \ 421 "echo PROGRAM SUCCEEDED; " \ 422 "fi; " \ 423 "else; " \ 424 "echo DOWNLOAD FAILED; " \ 425 "fi;" 426 427 #define CONFIG_PROG_UBOOT2 \ 428 "$download_cmd $loadaddr $ubootfile; " \ 429 "if test $? -eq 0; then " \ 430 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 431 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 432 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 433 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 434 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 435 "if test $? -ne 0; then " \ 436 "echo PROGRAM FAILED; " \ 437 "else; " \ 438 "echo PROGRAM SUCCEEDED; " \ 439 "fi; " \ 440 "else; " \ 441 "echo DOWNLOAD FAILED; " \ 442 "fi;" 443 444 #define CONFIG_BOOT_OS_NET \ 445 "$download_cmd $osaddr $osfile; " \ 446 "if test $? -eq 0; then " \ 447 "if test -n $fdtaddr; then " \ 448 "$download_cmd $fdtaddr $fdtfile; " \ 449 "if test $? -eq 0; then " \ 450 "bootm $osaddr - $fdtaddr; " \ 451 "else; " \ 452 "echo FDT DOWNLOAD FAILED; " \ 453 "fi; " \ 454 "else; " \ 455 "bootm $osaddr; " \ 456 "fi; " \ 457 "else; " \ 458 "echo OS DOWNLOAD FAILED; " \ 459 "fi;" 460 461 #define CONFIG_PROG_OS1 \ 462 "$download_cmd $osaddr $osfile; " \ 463 "if test $? -eq 0; then " \ 464 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 465 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 466 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 467 "if test $? -ne 0; then " \ 468 "echo OS PROGRAM FAILED; " \ 469 "else; " \ 470 "echo OS PROGRAM SUCCEEDED; " \ 471 "fi; " \ 472 "else; " \ 473 "echo OS DOWNLOAD FAILED; " \ 474 "fi;" 475 476 #define CONFIG_PROG_OS2 \ 477 "$download_cmd $osaddr $osfile; " \ 478 "if test $? -eq 0; then " \ 479 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 480 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 481 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 482 "if test $? -ne 0; then " \ 483 "echo OS PROGRAM FAILED; " \ 484 "else; " \ 485 "echo OS PROGRAM SUCCEEDED; " \ 486 "fi; " \ 487 "else; " \ 488 "echo OS DOWNLOAD FAILED; " \ 489 "fi;" 490 491 #define CONFIG_PROG_FDT1 \ 492 "$download_cmd $fdtaddr $fdtfile; " \ 493 "if test $? -eq 0; then " \ 494 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 495 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 496 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 497 "if test $? -ne 0; then " \ 498 "echo FDT PROGRAM FAILED; " \ 499 "else; " \ 500 "echo FDT PROGRAM SUCCEEDED; " \ 501 "fi; " \ 502 "else; " \ 503 "echo FDT DOWNLOAD FAILED; " \ 504 "fi;" 505 506 #define CONFIG_PROG_FDT2 \ 507 "$download_cmd $fdtaddr $fdtfile; " \ 508 "if test $? -eq 0; then " \ 509 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 510 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 511 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 512 "if test $? -ne 0; then " \ 513 "echo FDT PROGRAM FAILED; " \ 514 "else; " \ 515 "echo FDT PROGRAM SUCCEEDED; " \ 516 "fi; " \ 517 "else; " \ 518 "echo FDT DOWNLOAD FAILED; " \ 519 "fi;" 520 521 #define CONFIG_EXTRA_ENV_SETTINGS \ 522 "autoload=yes\0" \ 523 "download_cmd=tftp\0" \ 524 "console_args=console=ttyS0,115200\0" \ 525 "root_args=root=/dev/nfs rw\0" \ 526 "misc_args=ip=on\0" \ 527 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 528 "bootfile=/home/user/file\0" \ 529 "osfile=/home/user/board.uImage\0" \ 530 "fdtfile=/home/user/board.dtb\0" \ 531 "ubootfile=/home/user/u-boot.bin\0" \ 532 "fdtaddr=c00000\0" \ 533 "osaddr=0x1000000\0" \ 534 "loadaddr=0x1000000\0" \ 535 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 536 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 537 "prog_os1="CONFIG_PROG_OS1"\0" \ 538 "prog_os2="CONFIG_PROG_OS2"\0" \ 539 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 540 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 541 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 542 "bootcmd_flash1=run set_bootargs; " \ 543 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 544 "bootcmd_flash2=run set_bootargs; " \ 545 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 546 "bootcmd=run bootcmd_flash1\0" 547 #endif /* __CONFIG_H */ 548