1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2008 Extreme Engineering Solutions, Inc. 4 * Copyright 2004-2008 Freescale Semiconductor, Inc. 5 */ 6 7 /* 8 * xpedite520x board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 17 #define CONFIG_SYS_FORM_PMC_XMC 1 18 19 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 20 #define CONFIG_PCI1 1 /* PCI controller 1 */ 21 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 23 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 24 25 /* 26 * DDR config 27 */ 28 #undef CONFIG_FSL_DDR_INTERACTIVE 29 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 30 #define CONFIG_DDR_SPD 31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 32 #define SPD_EEPROM_ADDRESS 0x54 33 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 34 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 35 #define CONFIG_DDR_ECC 36 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 37 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 38 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 39 #define CONFIG_VERY_BIG_RAM 40 41 #define CONFIG_SYS_CLK_FREQ 66666666 42 43 /* 44 * These can be toggled for performance analysis, otherwise use default. 45 */ 46 #define CONFIG_L2_CACHE /* toggle L2 cache */ 47 #define CONFIG_BTB /* toggle branch predition */ 48 #define CONFIG_ENABLE_36BIT_PHYS 1 49 50 #define CONFIG_SYS_CCSRBAR 0xef000000 51 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 52 53 /* 54 * Diagnostics 55 */ 56 #define CONFIG_SYS_MEMTEST_START 0x10000000 57 #define CONFIG_SYS_MEMTEST_END 0x20000000 58 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 59 CONFIG_SYS_POST_I2C) 60 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ 61 CONFIG_SYS_I2C_EEPROM_ADDR, \ 62 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 63 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 64 CONFIG_SYS_I2C_RTC_ADDR} 65 66 /* 67 * Memory map 68 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 69 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 70 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 71 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 72 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 73 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 74 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 75 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 76 */ 77 78 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 79 80 /* 81 * NAND flash configuration 82 */ 83 #define CONFIG_SYS_NAND_BASE 0xef800000 84 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 85 #define CONFIG_SYS_MAX_NAND_DEVICE 1 86 #define CONFIG_NAND_ACTL 87 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 88 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 89 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 90 #define CONFIG_SYS_NAND_ACTL_DELAY 25 91 92 /* 93 * NOR flash configuration 94 */ 95 #define CONFIG_SYS_FLASH_BASE 0xfc000000 96 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 97 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 98 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 99 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 100 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 101 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 102 #define CONFIG_FLASH_CFI_DRIVER 103 #define CONFIG_SYS_FLASH_CFI 104 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 105 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 106 {0xfbf40000, 0xc0000} } 107 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 108 109 /* 110 * Chip select configuration 111 */ 112 /* NOR Flash 0 on CS0 */ 113 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 114 BR_PS_16 | \ 115 BR_V) 116 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 117 OR_GPCM_ACS_DIV4 | \ 118 OR_GPCM_SCY_8) 119 120 /* NOR Flash 1 on CS1 */ 121 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 122 BR_PS_16 | \ 123 BR_V) 124 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 125 126 /* NAND flash on CS2 */ 127 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 128 BR_PS_8 | \ 129 BR_V) 130 131 /* NAND flash on CS2 */ 132 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 133 OR_GPCM_BCTLD | \ 134 OR_GPCM_CSNT | \ 135 OR_GPCM_ACS_DIV4 | \ 136 OR_GPCM_SCY_4 | \ 137 OR_GPCM_TRLX | \ 138 OR_GPCM_EHTR) 139 140 /* NAND flash on CS3 */ 141 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 142 BR_PS_8 | \ 143 BR_V) 144 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 145 146 /* 147 * Use L1 as initial stack 148 */ 149 #define CONFIG_SYS_INIT_RAM_LOCK 1 150 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 151 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 152 153 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 154 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 155 156 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 157 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 158 159 /* 160 * Serial Port 161 */ 162 #define CONFIG_SYS_NS16550_SERIAL 163 #define CONFIG_SYS_NS16550_REG_SIZE 1 164 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 165 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 166 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 167 #define CONFIG_SYS_BAUDRATE_TABLE \ 168 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 169 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 170 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 171 172 /* 173 * I2C 174 */ 175 #define CONFIG_SYS_I2C 176 #define CONFIG_SYS_I2C_FSL 177 #define CONFIG_SYS_FSL_I2C_SPEED 400000 178 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 179 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 180 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 181 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 182 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 183 184 /* I2C EEPROM */ 185 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 186 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 187 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 188 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 189 190 /* I2C RTC */ 191 #define CONFIG_RTC_M41T11 1 192 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 193 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 194 195 /* GPIO */ 196 #define CONFIG_PCA953X 197 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 198 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 199 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 200 201 /* PCA957 @ 0x18 */ 202 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 203 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 204 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 205 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 206 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 207 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 208 #define CONFIG_SYS_PCA953X_MONARCH 0x40 209 #define CONFIG_SYS_PCA953X_EREADY 0x80 210 211 /* PCA957 @ 0x19 */ 212 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 213 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 214 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 215 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 216 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 217 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 218 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 219 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 220 221 /* 12-bit ADC used to measure CPU diode */ 222 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 223 224 /* 225 * General PCI 226 * Memory space is mapped 1-1, but I/O space must start from 0. 227 */ 228 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 229 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 230 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 231 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 232 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 233 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 234 235 /* 236 * Networking options 237 */ 238 #define CONFIG_MII 1 /* MII PHY management */ 239 #define CONFIG_ETHPRIME "eTSEC1" 240 241 #define CONFIG_TSEC1 1 242 #define CONFIG_TSEC1_NAME "eTSEC1" 243 #define TSEC1_FLAGS TSEC_GIGABIT 244 #define TSEC1_PHY_ADDR 1 245 #define TSEC1_PHYIDX 0 246 #define CONFIG_HAS_ETH0 247 248 #define CONFIG_TSEC2 1 249 #define CONFIG_TSEC2_NAME "eTSEC2" 250 #define TSEC2_FLAGS TSEC_GIGABIT 251 #define TSEC2_PHY_ADDR 2 252 #define TSEC2_PHYIDX 0 253 #define CONFIG_HAS_ETH1 254 255 #define CONFIG_TSEC3 1 256 #define CONFIG_TSEC3_NAME "eTSEC3" 257 #define TSEC3_FLAGS TSEC_GIGABIT 258 #define TSEC3_PHY_ADDR 3 259 #define TSEC3_PHYIDX 0 260 #define CONFIG_HAS_ETH2 261 262 #define CONFIG_TSEC4 1 263 #define CONFIG_TSEC4_NAME "eTSEC4" 264 #define TSEC4_FLAGS TSEC_GIGABIT 265 #define TSEC4_PHY_ADDR 4 266 #define TSEC4_PHYIDX 0 267 #define CONFIG_HAS_ETH3 268 269 /* 270 * BOOTP options 271 */ 272 #define CONFIG_BOOTP_BOOTFILESIZE 273 274 /* 275 * Miscellaneous configurable options 276 */ 277 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 278 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 279 #define CONFIG_PREBOOT /* enable preboot variable */ 280 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 281 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 282 283 /* 284 * For booting Linux, the board info and command line data 285 * have to be in the first 16 MB of memory, since this is 286 * the maximum mapped by the Linux kernel during initialization. 287 */ 288 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 289 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 290 291 /* 292 * Environment Configuration 293 */ 294 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 295 #define CONFIG_ENV_SIZE 0x8000 296 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 297 298 /* 299 * Flash memory map: 300 * fff80000 - ffffffff Pri U-Boot (512 KB) 301 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 302 * fff00000 - fff3ffff Pri FDT (256KB) 303 * fef00000 - ffefffff Pri OS image (16MB) 304 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 305 * 306 * fbf80000 - fbffffff Sec U-Boot (512 KB) 307 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 308 * fbf00000 - fbf3ffff Sec FDT (256KB) 309 * faf00000 - fbefffff Sec OS image (16MB) 310 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 311 */ 312 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 313 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) 314 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 315 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) 316 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 317 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) 318 319 #define CONFIG_PROG_UBOOT1 \ 320 "$download_cmd $loadaddr $ubootfile; " \ 321 "if test $? -eq 0; then " \ 322 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 323 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 324 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 325 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 326 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 327 "if test $? -ne 0; then " \ 328 "echo PROGRAM FAILED; " \ 329 "else; " \ 330 "echo PROGRAM SUCCEEDED; " \ 331 "fi; " \ 332 "else; " \ 333 "echo DOWNLOAD FAILED; " \ 334 "fi;" 335 336 #define CONFIG_PROG_UBOOT2 \ 337 "$download_cmd $loadaddr $ubootfile; " \ 338 "if test $? -eq 0; then " \ 339 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 340 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 341 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 342 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 343 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 344 "if test $? -ne 0; then " \ 345 "echo PROGRAM FAILED; " \ 346 "else; " \ 347 "echo PROGRAM SUCCEEDED; " \ 348 "fi; " \ 349 "else; " \ 350 "echo DOWNLOAD FAILED; " \ 351 "fi;" 352 353 #define CONFIG_BOOT_OS_NET \ 354 "$download_cmd $osaddr $osfile; " \ 355 "if test $? -eq 0; then " \ 356 "if test -n $fdtaddr; then " \ 357 "$download_cmd $fdtaddr $fdtfile; " \ 358 "if test $? -eq 0; then " \ 359 "bootm $osaddr - $fdtaddr; " \ 360 "else; " \ 361 "echo FDT DOWNLOAD FAILED; " \ 362 "fi; " \ 363 "else; " \ 364 "bootm $osaddr; " \ 365 "fi; " \ 366 "else; " \ 367 "echo OS DOWNLOAD FAILED; " \ 368 "fi;" 369 370 #define CONFIG_PROG_OS1 \ 371 "$download_cmd $osaddr $osfile; " \ 372 "if test $? -eq 0; then " \ 373 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 374 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 375 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 376 "if test $? -ne 0; then " \ 377 "echo OS PROGRAM FAILED; " \ 378 "else; " \ 379 "echo OS PROGRAM SUCCEEDED; " \ 380 "fi; " \ 381 "else; " \ 382 "echo OS DOWNLOAD FAILED; " \ 383 "fi;" 384 385 #define CONFIG_PROG_OS2 \ 386 "$download_cmd $osaddr $osfile; " \ 387 "if test $? -eq 0; then " \ 388 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 389 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 390 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 391 "if test $? -ne 0; then " \ 392 "echo OS PROGRAM FAILED; " \ 393 "else; " \ 394 "echo OS PROGRAM SUCCEEDED; " \ 395 "fi; " \ 396 "else; " \ 397 "echo OS DOWNLOAD FAILED; " \ 398 "fi;" 399 400 #define CONFIG_PROG_FDT1 \ 401 "$download_cmd $fdtaddr $fdtfile; " \ 402 "if test $? -eq 0; then " \ 403 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 404 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 405 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 406 "if test $? -ne 0; then " \ 407 "echo FDT PROGRAM FAILED; " \ 408 "else; " \ 409 "echo FDT PROGRAM SUCCEEDED; " \ 410 "fi; " \ 411 "else; " \ 412 "echo FDT DOWNLOAD FAILED; " \ 413 "fi;" 414 415 #define CONFIG_PROG_FDT2 \ 416 "$download_cmd $fdtaddr $fdtfile; " \ 417 "if test $? -eq 0; then " \ 418 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 419 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 420 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 421 "if test $? -ne 0; then " \ 422 "echo FDT PROGRAM FAILED; " \ 423 "else; " \ 424 "echo FDT PROGRAM SUCCEEDED; " \ 425 "fi; " \ 426 "else; " \ 427 "echo FDT DOWNLOAD FAILED; " \ 428 "fi;" 429 430 #define CONFIG_EXTRA_ENV_SETTINGS \ 431 "autoload=yes\0" \ 432 "download_cmd=tftp\0" \ 433 "console_args=console=ttyS0,115200\0" \ 434 "root_args=root=/dev/nfs rw\0" \ 435 "misc_args=ip=on\0" \ 436 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 437 "bootfile=/home/user/file\0" \ 438 "osfile=/home/user/board.uImage\0" \ 439 "fdtfile=/home/user/board.dtb\0" \ 440 "ubootfile=/home/user/u-boot.bin\0" \ 441 "fdtaddr=0x1e00000\0" \ 442 "osaddr=0x1000000\0" \ 443 "loadaddr=0x1000000\0" \ 444 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 445 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 446 "prog_os1="CONFIG_PROG_OS1"\0" \ 447 "prog_os2="CONFIG_PROG_OS2"\0" \ 448 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 449 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 450 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 451 "bootcmd_flash1=run set_bootargs; " \ 452 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 453 "bootcmd_flash2=run set_bootargs; " \ 454 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 455 "bootcmd=run bootcmd_flash1\0" 456 #endif /* __CONFIG_H */ 457