1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2004-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite520x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_XPEDITE5200	1
18 #define CONFIG_SYS_BOARD_NAME	"XPedite5200"
19 #define CONFIG_SYS_FORM_PMC_XMC	1
20 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
21 
22 #ifndef CONFIG_SYS_TEXT_BASE
23 #define CONFIG_SYS_TEXT_BASE	0xfff80000
24 #endif
25 
26 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
27 #define CONFIG_PCI1		1	/* PCI controller 1 */
28 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
29 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
30 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
31 
32 /*
33  * DDR config
34  */
35 #undef CONFIG_FSL_DDR_INTERACTIVE
36 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
37 #define CONFIG_DDR_SPD
38 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
39 #define SPD_EEPROM_ADDRESS		0x54
40 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
41 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
42 #define CONFIG_DDR_ECC
43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
44 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
45 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
46 #define CONFIG_VERY_BIG_RAM
47 
48 #define CONFIG_SYS_CLK_FREQ	66666666
49 
50 /*
51  * These can be toggled for performance analysis, otherwise use default.
52  */
53 #define CONFIG_L2_CACHE			/* toggle L2 cache */
54 #define CONFIG_BTB			/* toggle branch predition */
55 #define CONFIG_ENABLE_36BIT_PHYS	1
56 
57 #define CONFIG_SYS_CCSRBAR		0xef000000
58 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
59 
60 /*
61  * Diagnostics
62  */
63 #define CONFIG_SYS_ALT_MEMTEST
64 #define CONFIG_SYS_MEMTEST_START	0x10000000
65 #define CONFIG_SYS_MEMTEST_END		0x20000000
66 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
67 					 CONFIG_SYS_POST_I2C)
68 #define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
69 					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
70 					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
71 					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
72 					 CONFIG_SYS_I2C_RTC_ADDR}
73 
74 /*
75  * Memory map
76  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
77  * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
78  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
79  * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
80  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
81  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
82  * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
83  * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
84  */
85 
86 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
87 
88 /*
89  * NAND flash configuration
90  */
91 #define CONFIG_SYS_NAND_BASE		0xef800000
92 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
93 #define CONFIG_SYS_MAX_NAND_DEVICE	1
94 #define CONFIG_NAND_ACTL
95 #define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
96 #define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
97 #define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
98 #define CONFIG_SYS_NAND_ACTL_DELAY	25
99 
100 /*
101  * NOR flash configuration
102  */
103 #define CONFIG_SYS_FLASH_BASE		0xfc000000
104 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
105 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
106 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
107 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
108 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
109 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
110 #define CONFIG_FLASH_CFI_DRIVER
111 #define CONFIG_SYS_FLASH_CFI
112 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
113 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
114 						  {0xfbf40000, 0xc0000} }
115 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
116 
117 /*
118  * Chip select configuration
119  */
120 /* NOR Flash 0 on CS0 */
121 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
122 				 BR_PS_16		| \
123 				 BR_V)
124 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
125 				 OR_GPCM_ACS_DIV4	| \
126 				 OR_GPCM_SCY_8)
127 
128 /* NOR Flash 1 on CS1 */
129 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
130 				 BR_PS_16		| \
131 				 BR_V)
132 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
133 
134 /* NAND flash on CS2 */
135 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
136 				 BR_PS_8		| \
137 				 BR_V)
138 
139 /* NAND flash on CS2 */
140 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
141 				 OR_GPCM_BCTLD		| \
142 				 OR_GPCM_CSNT		| \
143 				 OR_GPCM_ACS_DIV4	| \
144 				 OR_GPCM_SCY_4		| \
145 				 OR_GPCM_TRLX		| \
146 				 OR_GPCM_EHTR)
147 
148 /* NAND flash on CS3 */
149 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
150 				 BR_PS_8		| \
151 				 BR_V)
152 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
153 
154 /*
155  * Use L1 as initial stack
156  */
157 #define CONFIG_SYS_INIT_RAM_LOCK	1
158 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
159 #define CONFIG_SYS_INIT_RAM_SIZE		0x4000
160 
161 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
162 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
163 
164 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
165 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
166 
167 /*
168  * Serial Port
169  */
170 #define CONFIG_CONS_INDEX		1
171 #define CONFIG_SYS_NS16550_SERIAL
172 #define CONFIG_SYS_NS16550_REG_SIZE	1
173 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
174 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
175 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
176 #define CONFIG_SYS_BAUDRATE_TABLE	\
177 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
178 #define CONFIG_BAUDRATE			115200
179 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
180 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
181 
182 /*
183  * I2C
184  */
185 #define CONFIG_SYS_I2C
186 #define CONFIG_SYS_I2C_FSL
187 #define CONFIG_SYS_FSL_I2C_SPEED	400000
188 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
189 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
190 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
191 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
192 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
193 
194 /* I2C EEPROM */
195 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
196 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
197 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
198 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
199 
200 /* I2C RTC */
201 #define CONFIG_RTC_M41T11			1
202 #define CONFIG_SYS_I2C_RTC_ADDR			0x68
203 #define CONFIG_SYS_M41T11_BASE_YEAR		2000
204 
205 /* GPIO */
206 #define CONFIG_PCA953X
207 #define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
208 #define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
209 #define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
210 
211 /* PCA957 @ 0x18 */
212 #define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
213 #define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
214 #define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
215 #define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
216 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
217 #define CONFIG_SYS_PCA953X_NVM_WP		0x20
218 #define CONFIG_SYS_PCA953X_MONARCH		0x40
219 #define CONFIG_SYS_PCA953X_EREADY		0x80
220 
221 /* PCA957 @ 0x19 */
222 #define CONFIG_SYS_PCA953X_P14_IO0		0x01
223 #define CONFIG_SYS_PCA953X_P14_IO1		0x02
224 #define CONFIG_SYS_PCA953X_P14_IO2		0x04
225 #define CONFIG_SYS_PCA953X_P14_IO3		0x08
226 #define CONFIG_SYS_PCA953X_P14_IO4		0x10
227 #define CONFIG_SYS_PCA953X_P14_IO5		0x20
228 #define CONFIG_SYS_PCA953X_P14_IO6		0x40
229 #define CONFIG_SYS_PCA953X_P14_IO7		0x80
230 
231 /* 12-bit ADC used to measure CPU diode */
232 #define CONFIG_SYS_I2C_MAX1237_ADDR		0x34
233 
234 /*
235  * General PCI
236  * Memory space is mapped 1-1, but I/O space must start from 0.
237  */
238 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
239 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
240 #define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
241 #define CONFIG_SYS_PCI1_IO_BUS		0x00000000
242 #define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
243 #define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
244 
245 /*
246  * Networking options
247  */
248 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
249 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
250 #define CONFIG_MII		1	/* MII PHY management */
251 #define CONFIG_ETHPRIME		"eTSEC1"
252 
253 #define CONFIG_TSEC1		1
254 #define CONFIG_TSEC1_NAME	"eTSEC1"
255 #define TSEC1_FLAGS		TSEC_GIGABIT
256 #define TSEC1_PHY_ADDR		1
257 #define TSEC1_PHYIDX		0
258 #define CONFIG_HAS_ETH0
259 
260 #define CONFIG_TSEC2		1
261 #define CONFIG_TSEC2_NAME	"eTSEC2"
262 #define TSEC2_FLAGS		TSEC_GIGABIT
263 #define TSEC2_PHY_ADDR		2
264 #define TSEC2_PHYIDX		0
265 #define CONFIG_HAS_ETH1
266 
267 #define CONFIG_TSEC3	1
268 #define CONFIG_TSEC3_NAME	"eTSEC3"
269 #define TSEC3_FLAGS		TSEC_GIGABIT
270 #define TSEC3_PHY_ADDR		3
271 #define TSEC3_PHYIDX		0
272 #define CONFIG_HAS_ETH2
273 
274 #define CONFIG_TSEC4	1
275 #define CONFIG_TSEC4_NAME	"eTSEC4"
276 #define TSEC4_FLAGS		TSEC_GIGABIT
277 #define TSEC4_PHY_ADDR		4
278 #define TSEC4_PHYIDX		0
279 #define CONFIG_HAS_ETH3
280 
281 /*
282  * BOOTP options
283  */
284 #define CONFIG_BOOTP_BOOTFILESIZE
285 #define CONFIG_BOOTP_BOOTPATH
286 #define CONFIG_BOOTP_GATEWAY
287 
288 /*
289  * Command configuration.
290  */
291 #define CONFIG_CMD_DATE
292 #define CONFIG_CMD_EEPROM
293 #define CONFIG_CMD_JFFS2
294 #define CONFIG_CMD_NAND
295 #define CONFIG_CMD_PCA953X
296 #define CONFIG_CMD_PCA953X_INFO
297 #define CONFIG_CMD_PCI
298 #define CONFIG_CMD_PCI_ENUM
299 #define CONFIG_CMD_REGINFO
300 
301 /*
302  * Miscellaneous configurable options
303  */
304 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
305 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
306 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
307 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
308 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
309 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
310 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
311 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
312 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
313 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
314 #define CONFIG_PREBOOT				/* enable preboot variable */
315 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
316 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
317 
318 /*
319  * For booting Linux, the board info and command line data
320  * have to be in the first 16 MB of memory, since this is
321  * the maximum mapped by the Linux kernel during initialization.
322  */
323 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
324 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
325 
326 /*
327  * Environment Configuration
328  */
329 #define CONFIG_ENV_IS_IN_FLASH	1
330 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
331 #define CONFIG_ENV_SIZE		0x8000
332 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
333 
334 /*
335  * Flash memory map:
336  * fff80000 - ffffffff     Pri U-Boot (512 KB)
337  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
338  * fff00000 - fff3ffff     Pri FDT (256KB)
339  * fef00000 - ffefffff     Pri OS image (16MB)
340  * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
341  *
342  * fbf80000 - fbffffff     Sec U-Boot (512 KB)
343  * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
344  * fbf00000 - fbf3ffff     Sec FDT (256KB)
345  * faf00000 - fbefffff     Sec OS image (16MB)
346  * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
347  */
348 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
349 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xfbf80000)
350 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
351 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xfbf00000)
352 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
353 #define CONFIG_OS2_ENV_ADDR	__stringify(0xfaf00000)
354 
355 #define CONFIG_PROG_UBOOT1						\
356 	"$download_cmd $loadaddr $ubootfile; "				\
357 	"if test $? -eq 0; then "					\
358 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
359 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
360 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
361 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
362 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
363 		"if test $? -ne 0; then "				\
364 			"echo PROGRAM FAILED; "				\
365 		"else; "						\
366 			"echo PROGRAM SUCCEEDED; "			\
367 		"fi; "							\
368 	"else; "							\
369 		"echo DOWNLOAD FAILED; "				\
370 	"fi;"
371 
372 #define CONFIG_PROG_UBOOT2						\
373 	"$download_cmd $loadaddr $ubootfile; "				\
374 	"if test $? -eq 0; then "					\
375 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
376 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
377 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
378 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
379 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
380 		"if test $? -ne 0; then "				\
381 			"echo PROGRAM FAILED; "				\
382 		"else; "						\
383 			"echo PROGRAM SUCCEEDED; "			\
384 		"fi; "							\
385 	"else; "							\
386 		"echo DOWNLOAD FAILED; "				\
387 	"fi;"
388 
389 #define CONFIG_BOOT_OS_NET						\
390 	"$download_cmd $osaddr $osfile; "				\
391 	"if test $? -eq 0; then "					\
392 		"if test -n $fdtaddr; then "				\
393 			"$download_cmd $fdtaddr $fdtfile; "		\
394 			"if test $? -eq 0; then "			\
395 				"bootm $osaddr - $fdtaddr; "		\
396 			"else; "					\
397 				"echo FDT DOWNLOAD FAILED; "		\
398 			"fi; "						\
399 		"else; "						\
400 			"bootm $osaddr; "				\
401 		"fi; "							\
402 	"else; "							\
403 		"echo OS DOWNLOAD FAILED; "				\
404 	"fi;"
405 
406 #define CONFIG_PROG_OS1							\
407 	"$download_cmd $osaddr $osfile; "				\
408 	"if test $? -eq 0; then "					\
409 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
410 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
411 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
412 		"if test $? -ne 0; then "				\
413 			"echo OS PROGRAM FAILED; "			\
414 		"else; "						\
415 			"echo OS PROGRAM SUCCEEDED; "			\
416 		"fi; "							\
417 	"else; "							\
418 		"echo OS DOWNLOAD FAILED; "				\
419 	"fi;"
420 
421 #define CONFIG_PROG_OS2							\
422 	"$download_cmd $osaddr $osfile; "				\
423 	"if test $? -eq 0; then "					\
424 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
425 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
426 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
427 		"if test $? -ne 0; then "				\
428 			"echo OS PROGRAM FAILED; "			\
429 		"else; "						\
430 			"echo OS PROGRAM SUCCEEDED; "			\
431 		"fi; "							\
432 	"else; "							\
433 		"echo OS DOWNLOAD FAILED; "				\
434 	"fi;"
435 
436 #define CONFIG_PROG_FDT1						\
437 	"$download_cmd $fdtaddr $fdtfile; "				\
438 	"if test $? -eq 0; then "					\
439 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
440 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
441 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
442 		"if test $? -ne 0; then "				\
443 			"echo FDT PROGRAM FAILED; "			\
444 		"else; "						\
445 			"echo FDT PROGRAM SUCCEEDED; "			\
446 		"fi; "							\
447 	"else; "							\
448 		"echo FDT DOWNLOAD FAILED; "				\
449 	"fi;"
450 
451 #define CONFIG_PROG_FDT2						\
452 	"$download_cmd $fdtaddr $fdtfile; "				\
453 	"if test $? -eq 0; then "					\
454 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
455 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
456 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
457 		"if test $? -ne 0; then "				\
458 			"echo FDT PROGRAM FAILED; "			\
459 		"else; "						\
460 			"echo FDT PROGRAM SUCCEEDED; "			\
461 		"fi; "							\
462 	"else; "							\
463 		"echo FDT DOWNLOAD FAILED; "				\
464 	"fi;"
465 
466 #define	CONFIG_EXTRA_ENV_SETTINGS					\
467 	"autoload=yes\0"						\
468 	"download_cmd=tftp\0"						\
469 	"console_args=console=ttyS0,115200\0"				\
470 	"root_args=root=/dev/nfs rw\0"					\
471 	"misc_args=ip=on\0"						\
472 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
473 	"bootfile=/home/user/file\0"					\
474 	"osfile=/home/user/board.uImage\0"				\
475 	"fdtfile=/home/user/board.dtb\0"				\
476 	"ubootfile=/home/user/u-boot.bin\0"				\
477 	"fdtaddr=0x1e00000\0"						\
478 	"osaddr=0x1000000\0"						\
479 	"loadaddr=0x1000000\0"						\
480 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
481 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
482 	"prog_os1="CONFIG_PROG_OS1"\0"					\
483 	"prog_os2="CONFIG_PROG_OS2"\0"					\
484 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
485 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
486 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
487 	"bootcmd_flash1=run set_bootargs; "				\
488 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
489 	"bootcmd_flash2=run set_bootargs; "				\
490 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
491 	"bootcmd=run bootcmd_flash1\0"
492 #endif	/* __CONFIG_H */
493