1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * xpedite520x board configuration file 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* 31 * High Level Configuration Options 32 */ 33 #define CONFIG_BOOKE 1 /* BOOKE */ 34 #define CONFIG_E500 1 /* BOOKE e500 family */ 35 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 36 #define CONFIG_MPC8548 1 37 #define CONFIG_XPEDITE5200 1 38 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 39 #define CONFIG_SYS_FORM_PMC_XMC 1 40 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 41 42 #ifndef CONFIG_SYS_TEXT_BASE 43 #define CONFIG_SYS_TEXT_BASE 0xfff80000 44 #endif 45 46 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 47 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ 48 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 49 #define CONFIG_PCI1 1 /* PCI controller 1 */ 50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 51 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 53 54 /* 55 * DDR config 56 */ 57 #define CONFIG_FSL_DDR2 58 #undef CONFIG_FSL_DDR_INTERACTIVE 59 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 60 #define CONFIG_DDR_SPD 61 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 62 #define SPD_EEPROM_ADDRESS 0x54 63 #define CONFIG_NUM_DDR_CONTROLLERS 1 64 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 65 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 66 #define CONFIG_DDR_ECC 67 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 68 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 69 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 70 #define CONFIG_VERY_BIG_RAM 71 72 #define CONFIG_SYS_CLK_FREQ 66666666 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE /* toggle L2 cache */ 78 #define CONFIG_BTB /* toggle branch predition */ 79 #define CONFIG_ENABLE_36BIT_PHYS 1 80 81 /* 82 * Base addresses -- Note these are effective addresses where the 83 * actual resources get mapped (not physical addresses) 84 */ 85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ 87 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 88 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 89 90 /* 91 * Diagnostics 92 */ 93 #define CONFIG_SYS_ALT_MEMTEST 94 #define CONFIG_SYS_MEMTEST_START 0x10000000 95 #define CONFIG_SYS_MEMTEST_END 0x20000000 96 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 97 CONFIG_SYS_POST_I2C) 98 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ 99 CONFIG_SYS_I2C_EEPROM_ADDR, \ 100 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 101 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 102 CONFIG_SYS_I2C_RTC_ADDR} 103 104 /* 105 * Memory map 106 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 107 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 108 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 109 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 110 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 111 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 112 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 113 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 114 */ 115 116 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 117 118 /* 119 * NAND flash configuration 120 */ 121 #define CONFIG_SYS_NAND_BASE 0xef800000 122 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 123 #define CONFIG_SYS_MAX_NAND_DEVICE 1 124 #define CONFIG_NAND_ACTL 125 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 126 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 127 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 128 #define CONFIG_SYS_NAND_ACTL_DELAY 25 129 130 /* 131 * NOR flash configuration 132 */ 133 #define CONFIG_SYS_FLASH_BASE 0xfc000000 134 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 135 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 136 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 137 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 138 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 139 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 140 #define CONFIG_FLASH_CFI_DRIVER 141 #define CONFIG_SYS_FLASH_CFI 142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 143 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 144 {0xfbf40000, 0xc0000} } 145 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 146 147 /* 148 * Chip select configuration 149 */ 150 /* NOR Flash 0 on CS0 */ 151 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 152 BR_PS_16 | \ 153 BR_V) 154 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 155 OR_GPCM_ACS_DIV4 | \ 156 OR_GPCM_SCY_8) 157 158 /* NOR Flash 1 on CS1 */ 159 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 160 BR_PS_16 | \ 161 BR_V) 162 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 163 164 /* NAND flash on CS2 */ 165 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 166 BR_PS_8 | \ 167 BR_V) 168 169 /* NAND flash on CS2 */ 170 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 171 OR_GPCM_BCTLD | \ 172 OR_GPCM_CSNT | \ 173 OR_GPCM_ACS_DIV4 | \ 174 OR_GPCM_SCY_4 | \ 175 OR_GPCM_TRLX | \ 176 OR_GPCM_EHTR) 177 178 /* NAND flash on CS3 */ 179 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 180 BR_PS_8 | \ 181 BR_V) 182 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 183 184 /* 185 * Use L1 as initial stack 186 */ 187 #define CONFIG_SYS_INIT_RAM_LOCK 1 188 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 189 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 190 191 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 192 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 193 194 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 195 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 196 197 /* 198 * Serial Port 199 */ 200 #define CONFIG_CONS_INDEX 1 201 #define CONFIG_SYS_NS16550 202 #define CONFIG_SYS_NS16550_SERIAL 203 #define CONFIG_SYS_NS16550_REG_SIZE 1 204 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 207 #define CONFIG_SYS_BAUDRATE_TABLE \ 208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 209 #define CONFIG_BAUDRATE 115200 210 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 211 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 212 213 /* 214 * Use the HUSH parser 215 */ 216 #define CONFIG_SYS_HUSH_PARSER 217 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 218 219 /* 220 * Pass open firmware flat tree 221 */ 222 #define CONFIG_OF_LIBFDT 1 223 #define CONFIG_OF_BOARD_SETUP 1 224 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 225 226 /* 227 * I2C 228 */ 229 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 230 #define CONFIG_HARD_I2C /* I2C with hardware support */ 231 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 232 #define CONFIG_SYS_I2C_SLAVE 0x7F 233 #define CONFIG_SYS_I2C_OFFSET 0x3000 234 #define CONFIG_SYS_I2C2_OFFSET 0x3100 235 #define CONFIG_I2C_MULTI_BUS 236 237 /* I2C EEPROM */ 238 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 239 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 242 243 /* I2C RTC */ 244 #define CONFIG_RTC_M41T11 1 245 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 246 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 247 248 /* GPIO */ 249 #define CONFIG_PCA953X 250 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 251 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 252 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 253 254 /* PCA957 @ 0x18 */ 255 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 256 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 257 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 258 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 259 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 260 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 261 #define CONFIG_SYS_PCA953X_MONARCH 0x40 262 #define CONFIG_SYS_PCA953X_EREADY 0x80 263 264 /* PCA957 @ 0x19 */ 265 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 266 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 267 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 268 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 269 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 270 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 271 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 272 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 273 274 /* 12-bit ADC used to measure CPU diode */ 275 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 276 277 /* 278 * General PCI 279 * Memory space is mapped 1-1, but I/O space must start from 0. 280 */ 281 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 282 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 283 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 284 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 285 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 286 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 287 288 /* 289 * Networking options 290 */ 291 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 292 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 293 #define CONFIG_NET_MULTI 1 294 #define CONFIG_MII 1 /* MII PHY management */ 295 #define CONFIG_ETHPRIME "eTSEC1" 296 297 #define CONFIG_TSEC1 1 298 #define CONFIG_TSEC1_NAME "eTSEC1" 299 #define TSEC1_FLAGS TSEC_GIGABIT 300 #define TSEC1_PHY_ADDR 1 301 #define TSEC1_PHYIDX 0 302 #define CONFIG_HAS_ETH0 303 304 #define CONFIG_TSEC2 1 305 #define CONFIG_TSEC2_NAME "eTSEC2" 306 #define TSEC2_FLAGS TSEC_GIGABIT 307 #define TSEC2_PHY_ADDR 2 308 #define TSEC2_PHYIDX 0 309 #define CONFIG_HAS_ETH1 310 311 #define CONFIG_TSEC3 1 312 #define CONFIG_TSEC3_NAME "eTSEC3" 313 #define TSEC3_FLAGS TSEC_GIGABIT 314 #define TSEC3_PHY_ADDR 3 315 #define TSEC3_PHYIDX 0 316 #define CONFIG_HAS_ETH2 317 318 #define CONFIG_TSEC4 1 319 #define CONFIG_TSEC4_NAME "eTSEC4" 320 #define TSEC4_FLAGS TSEC_GIGABIT 321 #define TSEC4_PHY_ADDR 4 322 #define TSEC4_PHYIDX 0 323 #define CONFIG_HAS_ETH3 324 325 /* 326 * BOOTP options 327 */ 328 #define CONFIG_BOOTP_BOOTFILESIZE 329 #define CONFIG_BOOTP_BOOTPATH 330 #define CONFIG_BOOTP_GATEWAY 331 332 /* 333 * Command configuration. 334 */ 335 #include <config_cmd_default.h> 336 337 #define CONFIG_CMD_ASKENV 338 #define CONFIG_CMD_DATE 339 #define CONFIG_CMD_DHCP 340 #define CONFIG_CMD_EEPROM 341 #define CONFIG_CMD_ELF 342 #define CONFIG_CMD_SAVEENV 343 #define CONFIG_CMD_FLASH 344 #define CONFIG_CMD_I2C 345 #define CONFIG_CMD_JFFS2 346 #define CONFIG_CMD_MII 347 #define CONFIG_CMD_NAND 348 #define CONFIG_CMD_NET 349 #define CONFIG_CMD_PCA953X 350 #define CONFIG_CMD_PCA953X_INFO 351 #define CONFIG_CMD_PCI 352 #define CONFIG_CMD_PCI_ENUM 353 #define CONFIG_CMD_PING 354 #define CONFIG_CMD_SNTP 355 #define CONFIG_CMD_REGINFO 356 357 /* 358 * Miscellaneous configurable options 359 */ 360 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 361 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 362 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 363 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 364 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 365 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 366 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 367 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 368 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 369 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 370 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 371 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ 372 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 373 #define CONFIG_PREBOOT /* enable preboot variable */ 374 #define CONFIG_FIT 1 375 #define CONFIG_FIT_VERBOSE 1 376 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 377 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 378 379 /* 380 * For booting Linux, the board info and command line data 381 * have to be in the first 16 MB of memory, since this is 382 * the maximum mapped by the Linux kernel during initialization. 383 */ 384 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 385 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 386 387 /* 388 * Environment Configuration 389 */ 390 #define CONFIG_ENV_IS_IN_FLASH 1 391 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 392 #define CONFIG_ENV_SIZE 0x8000 393 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 394 395 /* 396 * Flash memory map: 397 * fff80000 - ffffffff Pri U-Boot (512 KB) 398 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 399 * fff00000 - fff3ffff Pri FDT (256KB) 400 * fef00000 - ffefffff Pri OS image (16MB) 401 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 402 * 403 * fbf80000 - fbffffff Sec U-Boot (512 KB) 404 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 405 * fbf00000 - fbf3ffff Sec FDT (256KB) 406 * faf00000 - fbefffff Sec OS image (16MB) 407 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 408 */ 409 #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) 410 #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000) 411 #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) 412 #define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000) 413 #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) 414 #define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000) 415 416 #define CONFIG_PROG_UBOOT1 \ 417 "$download_cmd $loadaddr $ubootfile; " \ 418 "if test $? -eq 0; then " \ 419 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 420 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 421 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 422 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 423 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 424 "if test $? -ne 0; then " \ 425 "echo PROGRAM FAILED; " \ 426 "else; " \ 427 "echo PROGRAM SUCCEEDED; " \ 428 "fi; " \ 429 "else; " \ 430 "echo DOWNLOAD FAILED; " \ 431 "fi;" 432 433 #define CONFIG_PROG_UBOOT2 \ 434 "$download_cmd $loadaddr $ubootfile; " \ 435 "if test $? -eq 0; then " \ 436 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 437 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 438 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 439 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 440 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 441 "if test $? -ne 0; then " \ 442 "echo PROGRAM FAILED; " \ 443 "else; " \ 444 "echo PROGRAM SUCCEEDED; " \ 445 "fi; " \ 446 "else; " \ 447 "echo DOWNLOAD FAILED; " \ 448 "fi;" 449 450 #define CONFIG_BOOT_OS_NET \ 451 "$download_cmd $osaddr $osfile; " \ 452 "if test $? -eq 0; then " \ 453 "if test -n $fdtaddr; then " \ 454 "$download_cmd $fdtaddr $fdtfile; " \ 455 "if test $? -eq 0; then " \ 456 "bootm $osaddr - $fdtaddr; " \ 457 "else; " \ 458 "echo FDT DOWNLOAD FAILED; " \ 459 "fi; " \ 460 "else; " \ 461 "bootm $osaddr; " \ 462 "fi; " \ 463 "else; " \ 464 "echo OS DOWNLOAD FAILED; " \ 465 "fi;" 466 467 #define CONFIG_PROG_OS1 \ 468 "$download_cmd $osaddr $osfile; " \ 469 "if test $? -eq 0; then " \ 470 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 471 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 472 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 473 "if test $? -ne 0; then " \ 474 "echo OS PROGRAM FAILED; " \ 475 "else; " \ 476 "echo OS PROGRAM SUCCEEDED; " \ 477 "fi; " \ 478 "else; " \ 479 "echo OS DOWNLOAD FAILED; " \ 480 "fi;" 481 482 #define CONFIG_PROG_OS2 \ 483 "$download_cmd $osaddr $osfile; " \ 484 "if test $? -eq 0; then " \ 485 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 486 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 487 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 488 "if test $? -ne 0; then " \ 489 "echo OS PROGRAM FAILED; " \ 490 "else; " \ 491 "echo OS PROGRAM SUCCEEDED; " \ 492 "fi; " \ 493 "else; " \ 494 "echo OS DOWNLOAD FAILED; " \ 495 "fi;" 496 497 #define CONFIG_PROG_FDT1 \ 498 "$download_cmd $fdtaddr $fdtfile; " \ 499 "if test $? -eq 0; then " \ 500 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 501 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 502 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 503 "if test $? -ne 0; then " \ 504 "echo FDT PROGRAM FAILED; " \ 505 "else; " \ 506 "echo FDT PROGRAM SUCCEEDED; " \ 507 "fi; " \ 508 "else; " \ 509 "echo FDT DOWNLOAD FAILED; " \ 510 "fi;" 511 512 #define CONFIG_PROG_FDT2 \ 513 "$download_cmd $fdtaddr $fdtfile; " \ 514 "if test $? -eq 0; then " \ 515 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 516 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 517 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 518 "if test $? -ne 0; then " \ 519 "echo FDT PROGRAM FAILED; " \ 520 "else; " \ 521 "echo FDT PROGRAM SUCCEEDED; " \ 522 "fi; " \ 523 "else; " \ 524 "echo FDT DOWNLOAD FAILED; " \ 525 "fi;" 526 527 #define CONFIG_EXTRA_ENV_SETTINGS \ 528 "autoload=yes\0" \ 529 "download_cmd=tftp\0" \ 530 "console_args=console=ttyS0,115200\0" \ 531 "root_args=root=/dev/nfs rw\0" \ 532 "misc_args=ip=on\0" \ 533 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 534 "bootfile=/home/user/file\0" \ 535 "osfile=/home/user/board.uImage\0" \ 536 "fdtfile=/home/user/board.dtb\0" \ 537 "ubootfile=/home/user/u-boot.bin\0" \ 538 "fdtaddr=c00000\0" \ 539 "osaddr=0x1000000\0" \ 540 "loadaddr=0x1000000\0" \ 541 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 542 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 543 "prog_os1="CONFIG_PROG_OS1"\0" \ 544 "prog_os2="CONFIG_PROG_OS2"\0" \ 545 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 546 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 547 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 548 "bootcmd_flash1=run set_bootargs; " \ 549 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 550 "bootcmd_flash2=run set_bootargs; " \ 551 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 552 "bootcmd=run bootcmd_flash1\0" 553 #endif /* __CONFIG_H */ 554