1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2004-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite520x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_BOOKE		1	/* BOOKE */
18 #define CONFIG_E500		1	/* BOOKE e500 family */
19 #define CONFIG_MPC8548		1
20 #define CONFIG_XPEDITE5200	1
21 #define CONFIG_SYS_BOARD_NAME	"XPedite5200"
22 #define CONFIG_SYS_FORM_PMC_XMC	1
23 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
24 
25 #ifndef CONFIG_SYS_TEXT_BASE
26 #define CONFIG_SYS_TEXT_BASE	0xfff80000
27 #endif
28 
29 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
30 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
31 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
32 #define CONFIG_PCI1		1	/* PCI controller 1 */
33 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
34 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
35 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
36 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
37 
38 /*
39  * DDR config
40  */
41 #define CONFIG_SYS_FSL_DDR2
42 #undef CONFIG_FSL_DDR_INTERACTIVE
43 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
44 #define CONFIG_DDR_SPD
45 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
46 #define SPD_EEPROM_ADDRESS		0x54
47 #define CONFIG_NUM_DDR_CONTROLLERS	1
48 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
49 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
50 #define CONFIG_DDR_ECC
51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
52 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
53 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
54 #define CONFIG_VERY_BIG_RAM
55 
56 #define CONFIG_SYS_CLK_FREQ	66666666
57 
58 /*
59  * These can be toggled for performance analysis, otherwise use default.
60  */
61 #define CONFIG_L2_CACHE			/* toggle L2 cache */
62 #define CONFIG_BTB			/* toggle branch predition */
63 #define CONFIG_ENABLE_36BIT_PHYS	1
64 
65 #define CONFIG_SYS_CCSRBAR		0xef000000
66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
67 
68 /*
69  * Diagnostics
70  */
71 #define CONFIG_SYS_ALT_MEMTEST
72 #define CONFIG_SYS_MEMTEST_START	0x10000000
73 #define CONFIG_SYS_MEMTEST_END		0x20000000
74 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
75 					 CONFIG_SYS_POST_I2C)
76 #define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
77 					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
78 					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
79 					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
80 					 CONFIG_SYS_I2C_RTC_ADDR}
81 
82 /*
83  * Memory map
84  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
85  * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
86  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
87  * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
88  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
89  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
90  * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
91  * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
92  */
93 
94 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
95 
96 /*
97  * NAND flash configuration
98  */
99 #define CONFIG_SYS_NAND_BASE		0xef800000
100 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
101 #define CONFIG_SYS_MAX_NAND_DEVICE	1
102 #define CONFIG_NAND_ACTL
103 #define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
104 #define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
105 #define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
106 #define CONFIG_SYS_NAND_ACTL_DELAY	25
107 
108 /*
109  * NOR flash configuration
110  */
111 #define CONFIG_SYS_FLASH_BASE		0xfc000000
112 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
113 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
114 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
115 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
116 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
117 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
118 #define CONFIG_FLASH_CFI_DRIVER
119 #define CONFIG_SYS_FLASH_CFI
120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
121 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
122 						  {0xfbf40000, 0xc0000} }
123 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
124 
125 /*
126  * Chip select configuration
127  */
128 /* NOR Flash 0 on CS0 */
129 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
130 				 BR_PS_16		| \
131 				 BR_V)
132 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
133 				 OR_GPCM_ACS_DIV4	| \
134 				 OR_GPCM_SCY_8)
135 
136 /* NOR Flash 1 on CS1 */
137 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
138 				 BR_PS_16		| \
139 				 BR_V)
140 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
141 
142 /* NAND flash on CS2 */
143 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
144 				 BR_PS_8		| \
145 				 BR_V)
146 
147 /* NAND flash on CS2 */
148 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
149 				 OR_GPCM_BCTLD		| \
150 				 OR_GPCM_CSNT		| \
151 				 OR_GPCM_ACS_DIV4	| \
152 				 OR_GPCM_SCY_4		| \
153 				 OR_GPCM_TRLX		| \
154 				 OR_GPCM_EHTR)
155 
156 /* NAND flash on CS3 */
157 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
158 				 BR_PS_8		| \
159 				 BR_V)
160 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
161 
162 /*
163  * Use L1 as initial stack
164  */
165 #define CONFIG_SYS_INIT_RAM_LOCK	1
166 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
167 #define CONFIG_SYS_INIT_RAM_SIZE		0x4000
168 
169 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
170 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
171 
172 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
173 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
174 
175 /*
176  * Serial Port
177  */
178 #define CONFIG_CONS_INDEX		1
179 #define CONFIG_SYS_NS16550
180 #define CONFIG_SYS_NS16550_SERIAL
181 #define CONFIG_SYS_NS16550_REG_SIZE	1
182 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
183 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
184 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
185 #define CONFIG_SYS_BAUDRATE_TABLE	\
186 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
187 #define CONFIG_BAUDRATE			115200
188 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
189 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
190 
191 /*
192  * Use the HUSH parser
193  */
194 #define CONFIG_SYS_HUSH_PARSER
195 
196 /*
197  * Pass open firmware flat tree
198  */
199 #define CONFIG_OF_LIBFDT		1
200 #define CONFIG_OF_BOARD_SETUP		1
201 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
202 
203 /*
204  * I2C
205  */
206 #define CONFIG_SYS_I2C
207 #define CONFIG_SYS_I2C_FSL
208 #define CONFIG_SYS_FSL_I2C_SPEED	400000
209 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
210 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
211 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
212 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
213 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
214 
215 /* I2C EEPROM */
216 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
220 
221 /* I2C RTC */
222 #define CONFIG_RTC_M41T11			1
223 #define CONFIG_SYS_I2C_RTC_ADDR			0x68
224 #define CONFIG_SYS_M41T11_BASE_YEAR		2000
225 
226 /* GPIO */
227 #define CONFIG_PCA953X
228 #define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
229 #define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
230 #define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
231 
232 /* PCA957 @ 0x18 */
233 #define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
234 #define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
235 #define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
236 #define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
237 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
238 #define CONFIG_SYS_PCA953X_NVM_WP		0x20
239 #define CONFIG_SYS_PCA953X_MONARCH		0x40
240 #define CONFIG_SYS_PCA953X_EREADY		0x80
241 
242 /* PCA957 @ 0x19 */
243 #define CONFIG_SYS_PCA953X_P14_IO0		0x01
244 #define CONFIG_SYS_PCA953X_P14_IO1		0x02
245 #define CONFIG_SYS_PCA953X_P14_IO2		0x04
246 #define CONFIG_SYS_PCA953X_P14_IO3		0x08
247 #define CONFIG_SYS_PCA953X_P14_IO4		0x10
248 #define CONFIG_SYS_PCA953X_P14_IO5		0x20
249 #define CONFIG_SYS_PCA953X_P14_IO6		0x40
250 #define CONFIG_SYS_PCA953X_P14_IO7		0x80
251 
252 /* 12-bit ADC used to measure CPU diode */
253 #define CONFIG_SYS_I2C_MAX1237_ADDR		0x34
254 
255 /*
256  * General PCI
257  * Memory space is mapped 1-1, but I/O space must start from 0.
258  */
259 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
260 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
261 #define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
262 #define CONFIG_SYS_PCI1_IO_BUS		0x00000000
263 #define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
264 #define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
265 
266 /*
267  * Networking options
268  */
269 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
270 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
271 #define CONFIG_MII		1	/* MII PHY management */
272 #define CONFIG_ETHPRIME		"eTSEC1"
273 
274 #define CONFIG_TSEC1		1
275 #define CONFIG_TSEC1_NAME	"eTSEC1"
276 #define TSEC1_FLAGS		TSEC_GIGABIT
277 #define TSEC1_PHY_ADDR		1
278 #define TSEC1_PHYIDX		0
279 #define CONFIG_HAS_ETH0
280 
281 #define CONFIG_TSEC2		1
282 #define CONFIG_TSEC2_NAME	"eTSEC2"
283 #define TSEC2_FLAGS		TSEC_GIGABIT
284 #define TSEC2_PHY_ADDR		2
285 #define TSEC2_PHYIDX		0
286 #define CONFIG_HAS_ETH1
287 
288 #define CONFIG_TSEC3	1
289 #define CONFIG_TSEC3_NAME	"eTSEC3"
290 #define TSEC3_FLAGS		TSEC_GIGABIT
291 #define TSEC3_PHY_ADDR		3
292 #define TSEC3_PHYIDX		0
293 #define CONFIG_HAS_ETH2
294 
295 #define CONFIG_TSEC4	1
296 #define CONFIG_TSEC4_NAME	"eTSEC4"
297 #define TSEC4_FLAGS		TSEC_GIGABIT
298 #define TSEC4_PHY_ADDR		4
299 #define TSEC4_PHYIDX		0
300 #define CONFIG_HAS_ETH3
301 
302 /*
303  * BOOTP options
304  */
305 #define CONFIG_BOOTP_BOOTFILESIZE
306 #define CONFIG_BOOTP_BOOTPATH
307 #define CONFIG_BOOTP_GATEWAY
308 
309 /*
310  * Command configuration.
311  */
312 #include <config_cmd_default.h>
313 
314 #define CONFIG_CMD_ASKENV
315 #define CONFIG_CMD_DATE
316 #define CONFIG_CMD_DHCP
317 #define CONFIG_CMD_EEPROM
318 #define CONFIG_CMD_ELF
319 #define CONFIG_CMD_SAVEENV
320 #define CONFIG_CMD_FLASH
321 #define CONFIG_CMD_I2C
322 #define CONFIG_CMD_JFFS2
323 #define CONFIG_CMD_MII
324 #define CONFIG_CMD_NAND
325 #define CONFIG_CMD_NET
326 #define CONFIG_CMD_PCA953X
327 #define CONFIG_CMD_PCA953X_INFO
328 #define CONFIG_CMD_PCI
329 #define CONFIG_CMD_PCI_ENUM
330 #define CONFIG_CMD_PING
331 #define CONFIG_CMD_SNTP
332 #define CONFIG_CMD_REGINFO
333 
334 /*
335  * Miscellaneous configurable options
336  */
337 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
338 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
339 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
340 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
341 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
342 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
343 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
344 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
345 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
346 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
347 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
348 #define CONFIG_PREBOOT				/* enable preboot variable */
349 #define CONFIG_FIT		1
350 #define CONFIG_FIT_VERBOSE	1
351 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
352 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
353 
354 /*
355  * For booting Linux, the board info and command line data
356  * have to be in the first 16 MB of memory, since this is
357  * the maximum mapped by the Linux kernel during initialization.
358  */
359 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
360 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
361 
362 /*
363  * Environment Configuration
364  */
365 #define CONFIG_ENV_IS_IN_FLASH	1
366 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
367 #define CONFIG_ENV_SIZE		0x8000
368 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
369 
370 /*
371  * Flash memory map:
372  * fff80000 - ffffffff     Pri U-Boot (512 KB)
373  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
374  * fff00000 - fff3ffff     Pri FDT (256KB)
375  * fef00000 - ffefffff     Pri OS image (16MB)
376  * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
377  *
378  * fbf80000 - fbffffff     Sec U-Boot (512 KB)
379  * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
380  * fbf00000 - fbf3ffff     Sec FDT (256KB)
381  * faf00000 - fbefffff     Sec OS image (16MB)
382  * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
383  */
384 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
385 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xfbf80000)
386 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
387 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xfbf00000)
388 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
389 #define CONFIG_OS2_ENV_ADDR	__stringify(0xfaf00000)
390 
391 #define CONFIG_PROG_UBOOT1						\
392 	"$download_cmd $loadaddr $ubootfile; "				\
393 	"if test $? -eq 0; then "					\
394 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
395 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
396 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
397 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
398 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
399 		"if test $? -ne 0; then "				\
400 			"echo PROGRAM FAILED; "				\
401 		"else; "						\
402 			"echo PROGRAM SUCCEEDED; "			\
403 		"fi; "							\
404 	"else; "							\
405 		"echo DOWNLOAD FAILED; "				\
406 	"fi;"
407 
408 #define CONFIG_PROG_UBOOT2						\
409 	"$download_cmd $loadaddr $ubootfile; "				\
410 	"if test $? -eq 0; then "					\
411 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
412 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
413 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
414 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
415 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
416 		"if test $? -ne 0; then "				\
417 			"echo PROGRAM FAILED; "				\
418 		"else; "						\
419 			"echo PROGRAM SUCCEEDED; "			\
420 		"fi; "							\
421 	"else; "							\
422 		"echo DOWNLOAD FAILED; "				\
423 	"fi;"
424 
425 #define CONFIG_BOOT_OS_NET						\
426 	"$download_cmd $osaddr $osfile; "				\
427 	"if test $? -eq 0; then "					\
428 		"if test -n $fdtaddr; then "				\
429 			"$download_cmd $fdtaddr $fdtfile; "		\
430 			"if test $? -eq 0; then "			\
431 				"bootm $osaddr - $fdtaddr; "		\
432 			"else; "					\
433 				"echo FDT DOWNLOAD FAILED; "		\
434 			"fi; "						\
435 		"else; "						\
436 			"bootm $osaddr; "				\
437 		"fi; "							\
438 	"else; "							\
439 		"echo OS DOWNLOAD FAILED; "				\
440 	"fi;"
441 
442 #define CONFIG_PROG_OS1							\
443 	"$download_cmd $osaddr $osfile; "				\
444 	"if test $? -eq 0; then "					\
445 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
446 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
447 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
448 		"if test $? -ne 0; then "				\
449 			"echo OS PROGRAM FAILED; "			\
450 		"else; "						\
451 			"echo OS PROGRAM SUCCEEDED; "			\
452 		"fi; "							\
453 	"else; "							\
454 		"echo OS DOWNLOAD FAILED; "				\
455 	"fi;"
456 
457 #define CONFIG_PROG_OS2							\
458 	"$download_cmd $osaddr $osfile; "				\
459 	"if test $? -eq 0; then "					\
460 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
461 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
462 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
463 		"if test $? -ne 0; then "				\
464 			"echo OS PROGRAM FAILED; "			\
465 		"else; "						\
466 			"echo OS PROGRAM SUCCEEDED; "			\
467 		"fi; "							\
468 	"else; "							\
469 		"echo OS DOWNLOAD FAILED; "				\
470 	"fi;"
471 
472 #define CONFIG_PROG_FDT1						\
473 	"$download_cmd $fdtaddr $fdtfile; "				\
474 	"if test $? -eq 0; then "					\
475 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
476 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
477 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
478 		"if test $? -ne 0; then "				\
479 			"echo FDT PROGRAM FAILED; "			\
480 		"else; "						\
481 			"echo FDT PROGRAM SUCCEEDED; "			\
482 		"fi; "							\
483 	"else; "							\
484 		"echo FDT DOWNLOAD FAILED; "				\
485 	"fi;"
486 
487 #define CONFIG_PROG_FDT2						\
488 	"$download_cmd $fdtaddr $fdtfile; "				\
489 	"if test $? -eq 0; then "					\
490 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
491 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
492 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
493 		"if test $? -ne 0; then "				\
494 			"echo FDT PROGRAM FAILED; "			\
495 		"else; "						\
496 			"echo FDT PROGRAM SUCCEEDED; "			\
497 		"fi; "							\
498 	"else; "							\
499 		"echo FDT DOWNLOAD FAILED; "				\
500 	"fi;"
501 
502 #define	CONFIG_EXTRA_ENV_SETTINGS					\
503 	"autoload=yes\0"						\
504 	"download_cmd=tftp\0"						\
505 	"console_args=console=ttyS0,115200\0"				\
506 	"root_args=root=/dev/nfs rw\0"					\
507 	"misc_args=ip=on\0"						\
508 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
509 	"bootfile=/home/user/file\0"					\
510 	"osfile=/home/user/board.uImage\0"				\
511 	"fdtfile=/home/user/board.dtb\0"				\
512 	"ubootfile=/home/user/u-boot.bin\0"				\
513 	"fdtaddr=c00000\0"						\
514 	"osaddr=0x1000000\0"						\
515 	"loadaddr=0x1000000\0"						\
516 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
517 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
518 	"prog_os1="CONFIG_PROG_OS1"\0"					\
519 	"prog_os2="CONFIG_PROG_OS2"\0"					\
520 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
521 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
522 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
523 	"bootcmd_flash1=run set_bootargs; "				\
524 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
525 	"bootcmd_flash2=run set_bootargs; "				\
526 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
527 	"bootcmd=run bootcmd_flash1\0"
528 #endif	/* __CONFIG_H */
529