1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2004-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite520x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_BOOKE		1	/* BOOKE */
18 #define CONFIG_E500		1	/* BOOKE e500 family */
19 #define CONFIG_MPC8548		1
20 #define CONFIG_XPEDITE5200	1
21 #define CONFIG_SYS_BOARD_NAME	"XPedite5200"
22 #define CONFIG_SYS_FORM_PMC_XMC	1
23 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
24 #define CONFIG_SYS_GENERIC_BOARD
25 #define CONFIG_DISPLAY_BOARDINFO
26 
27 #ifndef CONFIG_SYS_TEXT_BASE
28 #define CONFIG_SYS_TEXT_BASE	0xfff80000
29 #endif
30 
31 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
32 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
33 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
34 #define CONFIG_PCI1		1	/* PCI controller 1 */
35 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
36 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
37 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
38 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
39 
40 /*
41  * DDR config
42  */
43 #define CONFIG_SYS_FSL_DDR2
44 #undef CONFIG_FSL_DDR_INTERACTIVE
45 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
46 #define CONFIG_DDR_SPD
47 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
48 #define SPD_EEPROM_ADDRESS		0x54
49 #define CONFIG_NUM_DDR_CONTROLLERS	1
50 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
51 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
52 #define CONFIG_DDR_ECC
53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
54 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
55 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
56 #define CONFIG_VERY_BIG_RAM
57 
58 #define CONFIG_SYS_CLK_FREQ	66666666
59 
60 /*
61  * These can be toggled for performance analysis, otherwise use default.
62  */
63 #define CONFIG_L2_CACHE			/* toggle L2 cache */
64 #define CONFIG_BTB			/* toggle branch predition */
65 #define CONFIG_ENABLE_36BIT_PHYS	1
66 
67 #define CONFIG_SYS_CCSRBAR		0xef000000
68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
69 
70 /*
71  * Diagnostics
72  */
73 #define CONFIG_SYS_ALT_MEMTEST
74 #define CONFIG_SYS_MEMTEST_START	0x10000000
75 #define CONFIG_SYS_MEMTEST_END		0x20000000
76 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
77 					 CONFIG_SYS_POST_I2C)
78 #define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
79 					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
80 					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
81 					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
82 					 CONFIG_SYS_I2C_RTC_ADDR}
83 
84 /*
85  * Memory map
86  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
87  * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
88  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
89  * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
90  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
91  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
92  * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
93  * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
94  */
95 
96 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
97 
98 /*
99  * NAND flash configuration
100  */
101 #define CONFIG_SYS_NAND_BASE		0xef800000
102 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
103 #define CONFIG_SYS_MAX_NAND_DEVICE	1
104 #define CONFIG_NAND_ACTL
105 #define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
106 #define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
107 #define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
108 #define CONFIG_SYS_NAND_ACTL_DELAY	25
109 
110 /*
111  * NOR flash configuration
112  */
113 #define CONFIG_SYS_FLASH_BASE		0xfc000000
114 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
115 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
116 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
117 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
118 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
119 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
120 #define CONFIG_FLASH_CFI_DRIVER
121 #define CONFIG_SYS_FLASH_CFI
122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
123 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
124 						  {0xfbf40000, 0xc0000} }
125 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
126 
127 /*
128  * Chip select configuration
129  */
130 /* NOR Flash 0 on CS0 */
131 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
132 				 BR_PS_16		| \
133 				 BR_V)
134 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
135 				 OR_GPCM_ACS_DIV4	| \
136 				 OR_GPCM_SCY_8)
137 
138 /* NOR Flash 1 on CS1 */
139 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
140 				 BR_PS_16		| \
141 				 BR_V)
142 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
143 
144 /* NAND flash on CS2 */
145 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
146 				 BR_PS_8		| \
147 				 BR_V)
148 
149 /* NAND flash on CS2 */
150 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
151 				 OR_GPCM_BCTLD		| \
152 				 OR_GPCM_CSNT		| \
153 				 OR_GPCM_ACS_DIV4	| \
154 				 OR_GPCM_SCY_4		| \
155 				 OR_GPCM_TRLX		| \
156 				 OR_GPCM_EHTR)
157 
158 /* NAND flash on CS3 */
159 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
160 				 BR_PS_8		| \
161 				 BR_V)
162 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
163 
164 /*
165  * Use L1 as initial stack
166  */
167 #define CONFIG_SYS_INIT_RAM_LOCK	1
168 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
169 #define CONFIG_SYS_INIT_RAM_SIZE		0x4000
170 
171 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
172 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
173 
174 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
175 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
176 
177 /*
178  * Serial Port
179  */
180 #define CONFIG_CONS_INDEX		1
181 #define CONFIG_SYS_NS16550
182 #define CONFIG_SYS_NS16550_SERIAL
183 #define CONFIG_SYS_NS16550_REG_SIZE	1
184 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
185 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
186 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
187 #define CONFIG_SYS_BAUDRATE_TABLE	\
188 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
189 #define CONFIG_BAUDRATE			115200
190 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
191 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
192 
193 /*
194  * Use the HUSH parser
195  */
196 #define CONFIG_SYS_HUSH_PARSER
197 
198 /*
199  * Pass open firmware flat tree
200  */
201 #define CONFIG_OF_LIBFDT		1
202 #define CONFIG_OF_BOARD_SETUP		1
203 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
204 
205 /*
206  * I2C
207  */
208 #define CONFIG_SYS_I2C
209 #define CONFIG_SYS_I2C_FSL
210 #define CONFIG_SYS_FSL_I2C_SPEED	400000
211 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
212 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
213 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
214 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
215 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
216 
217 /* I2C EEPROM */
218 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
219 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
222 
223 /* I2C RTC */
224 #define CONFIG_RTC_M41T11			1
225 #define CONFIG_SYS_I2C_RTC_ADDR			0x68
226 #define CONFIG_SYS_M41T11_BASE_YEAR		2000
227 
228 /* GPIO */
229 #define CONFIG_PCA953X
230 #define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
231 #define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
232 #define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
233 
234 /* PCA957 @ 0x18 */
235 #define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
236 #define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
237 #define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
238 #define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
239 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
240 #define CONFIG_SYS_PCA953X_NVM_WP		0x20
241 #define CONFIG_SYS_PCA953X_MONARCH		0x40
242 #define CONFIG_SYS_PCA953X_EREADY		0x80
243 
244 /* PCA957 @ 0x19 */
245 #define CONFIG_SYS_PCA953X_P14_IO0		0x01
246 #define CONFIG_SYS_PCA953X_P14_IO1		0x02
247 #define CONFIG_SYS_PCA953X_P14_IO2		0x04
248 #define CONFIG_SYS_PCA953X_P14_IO3		0x08
249 #define CONFIG_SYS_PCA953X_P14_IO4		0x10
250 #define CONFIG_SYS_PCA953X_P14_IO5		0x20
251 #define CONFIG_SYS_PCA953X_P14_IO6		0x40
252 #define CONFIG_SYS_PCA953X_P14_IO7		0x80
253 
254 /* 12-bit ADC used to measure CPU diode */
255 #define CONFIG_SYS_I2C_MAX1237_ADDR		0x34
256 
257 /*
258  * General PCI
259  * Memory space is mapped 1-1, but I/O space must start from 0.
260  */
261 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
262 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
263 #define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
264 #define CONFIG_SYS_PCI1_IO_BUS		0x00000000
265 #define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
266 #define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
267 
268 /*
269  * Networking options
270  */
271 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
272 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
273 #define CONFIG_MII		1	/* MII PHY management */
274 #define CONFIG_ETHPRIME		"eTSEC1"
275 
276 #define CONFIG_TSEC1		1
277 #define CONFIG_TSEC1_NAME	"eTSEC1"
278 #define TSEC1_FLAGS		TSEC_GIGABIT
279 #define TSEC1_PHY_ADDR		1
280 #define TSEC1_PHYIDX		0
281 #define CONFIG_HAS_ETH0
282 
283 #define CONFIG_TSEC2		1
284 #define CONFIG_TSEC2_NAME	"eTSEC2"
285 #define TSEC2_FLAGS		TSEC_GIGABIT
286 #define TSEC2_PHY_ADDR		2
287 #define TSEC2_PHYIDX		0
288 #define CONFIG_HAS_ETH1
289 
290 #define CONFIG_TSEC3	1
291 #define CONFIG_TSEC3_NAME	"eTSEC3"
292 #define TSEC3_FLAGS		TSEC_GIGABIT
293 #define TSEC3_PHY_ADDR		3
294 #define TSEC3_PHYIDX		0
295 #define CONFIG_HAS_ETH2
296 
297 #define CONFIG_TSEC4	1
298 #define CONFIG_TSEC4_NAME	"eTSEC4"
299 #define TSEC4_FLAGS		TSEC_GIGABIT
300 #define TSEC4_PHY_ADDR		4
301 #define TSEC4_PHYIDX		0
302 #define CONFIG_HAS_ETH3
303 
304 /*
305  * BOOTP options
306  */
307 #define CONFIG_BOOTP_BOOTFILESIZE
308 #define CONFIG_BOOTP_BOOTPATH
309 #define CONFIG_BOOTP_GATEWAY
310 
311 /*
312  * Command configuration.
313  */
314 #define CONFIG_CMD_ASKENV
315 #define CONFIG_CMD_DATE
316 #define CONFIG_CMD_DHCP
317 #define CONFIG_CMD_EEPROM
318 #define CONFIG_CMD_ELF
319 #define CONFIG_CMD_I2C
320 #define CONFIG_CMD_JFFS2
321 #define CONFIG_CMD_MII
322 #define CONFIG_CMD_NAND
323 #define CONFIG_CMD_PCA953X
324 #define CONFIG_CMD_PCA953X_INFO
325 #define CONFIG_CMD_PCI
326 #define CONFIG_CMD_PCI_ENUM
327 #define CONFIG_CMD_PING
328 #define CONFIG_CMD_SNTP
329 #define CONFIG_CMD_REGINFO
330 
331 /*
332  * Miscellaneous configurable options
333  */
334 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
335 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
336 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
337 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
338 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
339 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
340 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
341 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
342 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
343 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
344 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
345 #define CONFIG_PREBOOT				/* enable preboot variable */
346 #define CONFIG_FIT		1
347 #define CONFIG_FIT_VERBOSE	1
348 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
349 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
350 
351 /*
352  * For booting Linux, the board info and command line data
353  * have to be in the first 16 MB of memory, since this is
354  * the maximum mapped by the Linux kernel during initialization.
355  */
356 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
357 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
358 
359 /*
360  * Environment Configuration
361  */
362 #define CONFIG_ENV_IS_IN_FLASH	1
363 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
364 #define CONFIG_ENV_SIZE		0x8000
365 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
366 
367 /*
368  * Flash memory map:
369  * fff80000 - ffffffff     Pri U-Boot (512 KB)
370  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
371  * fff00000 - fff3ffff     Pri FDT (256KB)
372  * fef00000 - ffefffff     Pri OS image (16MB)
373  * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
374  *
375  * fbf80000 - fbffffff     Sec U-Boot (512 KB)
376  * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
377  * fbf00000 - fbf3ffff     Sec FDT (256KB)
378  * faf00000 - fbefffff     Sec OS image (16MB)
379  * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
380  */
381 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
382 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xfbf80000)
383 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
384 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xfbf00000)
385 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
386 #define CONFIG_OS2_ENV_ADDR	__stringify(0xfaf00000)
387 
388 #define CONFIG_PROG_UBOOT1						\
389 	"$download_cmd $loadaddr $ubootfile; "				\
390 	"if test $? -eq 0; then "					\
391 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
392 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
393 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
394 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
395 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
396 		"if test $? -ne 0; then "				\
397 			"echo PROGRAM FAILED; "				\
398 		"else; "						\
399 			"echo PROGRAM SUCCEEDED; "			\
400 		"fi; "							\
401 	"else; "							\
402 		"echo DOWNLOAD FAILED; "				\
403 	"fi;"
404 
405 #define CONFIG_PROG_UBOOT2						\
406 	"$download_cmd $loadaddr $ubootfile; "				\
407 	"if test $? -eq 0; then "					\
408 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
409 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
410 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
411 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
412 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
413 		"if test $? -ne 0; then "				\
414 			"echo PROGRAM FAILED; "				\
415 		"else; "						\
416 			"echo PROGRAM SUCCEEDED; "			\
417 		"fi; "							\
418 	"else; "							\
419 		"echo DOWNLOAD FAILED; "				\
420 	"fi;"
421 
422 #define CONFIG_BOOT_OS_NET						\
423 	"$download_cmd $osaddr $osfile; "				\
424 	"if test $? -eq 0; then "					\
425 		"if test -n $fdtaddr; then "				\
426 			"$download_cmd $fdtaddr $fdtfile; "		\
427 			"if test $? -eq 0; then "			\
428 				"bootm $osaddr - $fdtaddr; "		\
429 			"else; "					\
430 				"echo FDT DOWNLOAD FAILED; "		\
431 			"fi; "						\
432 		"else; "						\
433 			"bootm $osaddr; "				\
434 		"fi; "							\
435 	"else; "							\
436 		"echo OS DOWNLOAD FAILED; "				\
437 	"fi;"
438 
439 #define CONFIG_PROG_OS1							\
440 	"$download_cmd $osaddr $osfile; "				\
441 	"if test $? -eq 0; then "					\
442 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
443 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
444 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
445 		"if test $? -ne 0; then "				\
446 			"echo OS PROGRAM FAILED; "			\
447 		"else; "						\
448 			"echo OS PROGRAM SUCCEEDED; "			\
449 		"fi; "							\
450 	"else; "							\
451 		"echo OS DOWNLOAD FAILED; "				\
452 	"fi;"
453 
454 #define CONFIG_PROG_OS2							\
455 	"$download_cmd $osaddr $osfile; "				\
456 	"if test $? -eq 0; then "					\
457 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
458 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
459 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
460 		"if test $? -ne 0; then "				\
461 			"echo OS PROGRAM FAILED; "			\
462 		"else; "						\
463 			"echo OS PROGRAM SUCCEEDED; "			\
464 		"fi; "							\
465 	"else; "							\
466 		"echo OS DOWNLOAD FAILED; "				\
467 	"fi;"
468 
469 #define CONFIG_PROG_FDT1						\
470 	"$download_cmd $fdtaddr $fdtfile; "				\
471 	"if test $? -eq 0; then "					\
472 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
473 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
474 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
475 		"if test $? -ne 0; then "				\
476 			"echo FDT PROGRAM FAILED; "			\
477 		"else; "						\
478 			"echo FDT PROGRAM SUCCEEDED; "			\
479 		"fi; "							\
480 	"else; "							\
481 		"echo FDT DOWNLOAD FAILED; "				\
482 	"fi;"
483 
484 #define CONFIG_PROG_FDT2						\
485 	"$download_cmd $fdtaddr $fdtfile; "				\
486 	"if test $? -eq 0; then "					\
487 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
488 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
489 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
490 		"if test $? -ne 0; then "				\
491 			"echo FDT PROGRAM FAILED; "			\
492 		"else; "						\
493 			"echo FDT PROGRAM SUCCEEDED; "			\
494 		"fi; "							\
495 	"else; "							\
496 		"echo FDT DOWNLOAD FAILED; "				\
497 	"fi;"
498 
499 #define	CONFIG_EXTRA_ENV_SETTINGS					\
500 	"autoload=yes\0"						\
501 	"download_cmd=tftp\0"						\
502 	"console_args=console=ttyS0,115200\0"				\
503 	"root_args=root=/dev/nfs rw\0"					\
504 	"misc_args=ip=on\0"						\
505 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
506 	"bootfile=/home/user/file\0"					\
507 	"osfile=/home/user/board.uImage\0"				\
508 	"fdtfile=/home/user/board.dtb\0"				\
509 	"ubootfile=/home/user/u-boot.bin\0"				\
510 	"fdtaddr=c00000\0"						\
511 	"osaddr=0x1000000\0"						\
512 	"loadaddr=0x1000000\0"						\
513 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
514 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
515 	"prog_os1="CONFIG_PROG_OS1"\0"					\
516 	"prog_os2="CONFIG_PROG_OS2"\0"					\
517 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
518 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
519 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
520 	"bootcmd_flash1=run set_bootargs; "				\
521 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
522 	"bootcmd_flash2=run set_bootargs; "				\
523 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
524 	"bootcmd=run bootcmd_flash1\0"
525 #endif	/* __CONFIG_H */
526