1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2004-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite520x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_XPEDITE5200 1 20 #define CONFIG_SYS_BOARD_NAME "XPedite5200" 21 #define CONFIG_SYS_FORM_PMC_XMC 1 22 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 23 24 #ifndef CONFIG_SYS_TEXT_BASE 25 #define CONFIG_SYS_TEXT_BASE 0xfff80000 26 #endif 27 28 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 29 #define CONFIG_PCI1 1 /* PCI controller 1 */ 30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 33 34 /* 35 * DDR config 36 */ 37 #define CONFIG_SYS_FSL_DDR2 38 #undef CONFIG_FSL_DDR_INTERACTIVE 39 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 40 #define CONFIG_DDR_SPD 41 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 42 #define SPD_EEPROM_ADDRESS 0x54 43 #define CONFIG_NUM_DDR_CONTROLLERS 1 44 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 45 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 46 #define CONFIG_DDR_ECC 47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 50 #define CONFIG_VERY_BIG_RAM 51 52 #define CONFIG_SYS_CLK_FREQ 66666666 53 54 /* 55 * These can be toggled for performance analysis, otherwise use default. 56 */ 57 #define CONFIG_L2_CACHE /* toggle L2 cache */ 58 #define CONFIG_BTB /* toggle branch predition */ 59 #define CONFIG_ENABLE_36BIT_PHYS 1 60 61 #define CONFIG_SYS_CCSRBAR 0xef000000 62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 63 64 /* 65 * Diagnostics 66 */ 67 #define CONFIG_SYS_ALT_MEMTEST 68 #define CONFIG_SYS_MEMTEST_START 0x10000000 69 #define CONFIG_SYS_MEMTEST_END 0x20000000 70 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 71 CONFIG_SYS_POST_I2C) 72 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ 73 CONFIG_SYS_I2C_EEPROM_ADDR, \ 74 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 75 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 76 CONFIG_SYS_I2C_RTC_ADDR} 77 78 /* 79 * Memory map 80 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 81 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable 82 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 83 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable 84 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 85 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 86 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable 87 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable 88 */ 89 90 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) 91 92 /* 93 * NAND flash configuration 94 */ 95 #define CONFIG_SYS_NAND_BASE 0xef800000 96 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 97 #define CONFIG_SYS_MAX_NAND_DEVICE 1 98 #define CONFIG_NAND_ACTL 99 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ 100 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ 101 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ 102 #define CONFIG_SYS_NAND_ACTL_DELAY 25 103 104 /* 105 * NOR flash configuration 106 */ 107 #define CONFIG_SYS_FLASH_BASE 0xfc000000 108 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 109 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 110 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 111 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 114 #define CONFIG_FLASH_CFI_DRIVER 115 #define CONFIG_SYS_FLASH_CFI 116 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 117 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ 118 {0xfbf40000, 0xc0000} } 119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 120 121 /* 122 * Chip select configuration 123 */ 124 /* NOR Flash 0 on CS0 */ 125 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 126 BR_PS_16 | \ 127 BR_V) 128 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ 129 OR_GPCM_ACS_DIV4 | \ 130 OR_GPCM_SCY_8) 131 132 /* NOR Flash 1 on CS1 */ 133 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ 134 BR_PS_16 | \ 135 BR_V) 136 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 137 138 /* NAND flash on CS2 */ 139 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ 140 BR_PS_8 | \ 141 BR_V) 142 143 /* NAND flash on CS2 */ 144 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ 145 OR_GPCM_BCTLD | \ 146 OR_GPCM_CSNT | \ 147 OR_GPCM_ACS_DIV4 | \ 148 OR_GPCM_SCY_4 | \ 149 OR_GPCM_TRLX | \ 150 OR_GPCM_EHTR) 151 152 /* NAND flash on CS3 */ 153 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ 154 BR_PS_8 | \ 155 BR_V) 156 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 157 158 /* 159 * Use L1 as initial stack 160 */ 161 #define CONFIG_SYS_INIT_RAM_LOCK 1 162 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 163 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 164 165 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 166 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 167 168 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 169 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 170 171 /* 172 * Serial Port 173 */ 174 #define CONFIG_CONS_INDEX 1 175 #define CONFIG_SYS_NS16550_SERIAL 176 #define CONFIG_SYS_NS16550_REG_SIZE 1 177 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 180 #define CONFIG_SYS_BAUDRATE_TABLE \ 181 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 182 #define CONFIG_BAUDRATE 115200 183 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 184 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 185 186 /* 187 * I2C 188 */ 189 #define CONFIG_SYS_I2C 190 #define CONFIG_SYS_I2C_FSL 191 #define CONFIG_SYS_FSL_I2C_SPEED 400000 192 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 193 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 194 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 195 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 196 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 197 198 /* I2C EEPROM */ 199 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 200 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 201 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 202 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 203 204 /* I2C RTC */ 205 #define CONFIG_RTC_M41T11 1 206 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 207 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 208 209 /* GPIO */ 210 #define CONFIG_PCA953X 211 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 212 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 213 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 214 215 /* PCA957 @ 0x18 */ 216 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 217 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 218 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 219 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 220 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 221 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 222 #define CONFIG_SYS_PCA953X_MONARCH 0x40 223 #define CONFIG_SYS_PCA953X_EREADY 0x80 224 225 /* PCA957 @ 0x19 */ 226 #define CONFIG_SYS_PCA953X_P14_IO0 0x01 227 #define CONFIG_SYS_PCA953X_P14_IO1 0x02 228 #define CONFIG_SYS_PCA953X_P14_IO2 0x04 229 #define CONFIG_SYS_PCA953X_P14_IO3 0x08 230 #define CONFIG_SYS_PCA953X_P14_IO4 0x10 231 #define CONFIG_SYS_PCA953X_P14_IO5 0x20 232 #define CONFIG_SYS_PCA953X_P14_IO6 0x40 233 #define CONFIG_SYS_PCA953X_P14_IO7 0x80 234 235 /* 12-bit ADC used to measure CPU diode */ 236 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 237 238 /* 239 * General PCI 240 * Memory space is mapped 1-1, but I/O space must start from 0. 241 */ 242 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 243 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 244 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ 245 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 246 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 247 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ 248 249 /* 250 * Networking options 251 */ 252 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 253 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 254 #define CONFIG_MII 1 /* MII PHY management */ 255 #define CONFIG_ETHPRIME "eTSEC1" 256 257 #define CONFIG_TSEC1 1 258 #define CONFIG_TSEC1_NAME "eTSEC1" 259 #define TSEC1_FLAGS TSEC_GIGABIT 260 #define TSEC1_PHY_ADDR 1 261 #define TSEC1_PHYIDX 0 262 #define CONFIG_HAS_ETH0 263 264 #define CONFIG_TSEC2 1 265 #define CONFIG_TSEC2_NAME "eTSEC2" 266 #define TSEC2_FLAGS TSEC_GIGABIT 267 #define TSEC2_PHY_ADDR 2 268 #define TSEC2_PHYIDX 0 269 #define CONFIG_HAS_ETH1 270 271 #define CONFIG_TSEC3 1 272 #define CONFIG_TSEC3_NAME "eTSEC3" 273 #define TSEC3_FLAGS TSEC_GIGABIT 274 #define TSEC3_PHY_ADDR 3 275 #define TSEC3_PHYIDX 0 276 #define CONFIG_HAS_ETH2 277 278 #define CONFIG_TSEC4 1 279 #define CONFIG_TSEC4_NAME "eTSEC4" 280 #define TSEC4_FLAGS TSEC_GIGABIT 281 #define TSEC4_PHY_ADDR 4 282 #define TSEC4_PHYIDX 0 283 #define CONFIG_HAS_ETH3 284 285 /* 286 * BOOTP options 287 */ 288 #define CONFIG_BOOTP_BOOTFILESIZE 289 #define CONFIG_BOOTP_BOOTPATH 290 #define CONFIG_BOOTP_GATEWAY 291 292 /* 293 * Command configuration. 294 */ 295 #define CONFIG_CMD_DATE 296 #define CONFIG_CMD_EEPROM 297 #define CONFIG_CMD_JFFS2 298 #define CONFIG_CMD_NAND 299 #define CONFIG_CMD_PCA953X 300 #define CONFIG_CMD_PCA953X_INFO 301 #define CONFIG_CMD_PCI 302 #define CONFIG_CMD_PCI_ENUM 303 #define CONFIG_CMD_REGINFO 304 305 /* 306 * Miscellaneous configurable options 307 */ 308 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 309 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 310 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 311 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 312 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 313 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 314 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 315 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 316 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 317 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 318 #define CONFIG_PREBOOT /* enable preboot variable */ 319 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 320 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 321 322 /* 323 * For booting Linux, the board info and command line data 324 * have to be in the first 16 MB of memory, since this is 325 * the maximum mapped by the Linux kernel during initialization. 326 */ 327 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 328 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 329 330 /* 331 * Environment Configuration 332 */ 333 #define CONFIG_ENV_IS_IN_FLASH 1 334 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 335 #define CONFIG_ENV_SIZE 0x8000 336 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) 337 338 /* 339 * Flash memory map: 340 * fff80000 - ffffffff Pri U-Boot (512 KB) 341 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) 342 * fff00000 - fff3ffff Pri FDT (256KB) 343 * fef00000 - ffefffff Pri OS image (16MB) 344 * fc000000 - feefffff Pri OS Use/Filesystem (47MB) 345 * 346 * fbf80000 - fbffffff Sec U-Boot (512 KB) 347 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) 348 * fbf00000 - fbf3ffff Sec FDT (256KB) 349 * faf00000 - fbefffff Sec OS image (16MB) 350 * f8000000 - faefffff Sec OS Use/Filesystem (47MB) 351 */ 352 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) 353 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) 354 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) 355 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) 356 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 357 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) 358 359 #define CONFIG_PROG_UBOOT1 \ 360 "$download_cmd $loadaddr $ubootfile; " \ 361 "if test $? -eq 0; then " \ 362 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 363 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 364 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 365 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 366 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 367 "if test $? -ne 0; then " \ 368 "echo PROGRAM FAILED; " \ 369 "else; " \ 370 "echo PROGRAM SUCCEEDED; " \ 371 "fi; " \ 372 "else; " \ 373 "echo DOWNLOAD FAILED; " \ 374 "fi;" 375 376 #define CONFIG_PROG_UBOOT2 \ 377 "$download_cmd $loadaddr $ubootfile; " \ 378 "if test $? -eq 0; then " \ 379 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 380 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 381 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 382 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 383 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 384 "if test $? -ne 0; then " \ 385 "echo PROGRAM FAILED; " \ 386 "else; " \ 387 "echo PROGRAM SUCCEEDED; " \ 388 "fi; " \ 389 "else; " \ 390 "echo DOWNLOAD FAILED; " \ 391 "fi;" 392 393 #define CONFIG_BOOT_OS_NET \ 394 "$download_cmd $osaddr $osfile; " \ 395 "if test $? -eq 0; then " \ 396 "if test -n $fdtaddr; then " \ 397 "$download_cmd $fdtaddr $fdtfile; " \ 398 "if test $? -eq 0; then " \ 399 "bootm $osaddr - $fdtaddr; " \ 400 "else; " \ 401 "echo FDT DOWNLOAD FAILED; " \ 402 "fi; " \ 403 "else; " \ 404 "bootm $osaddr; " \ 405 "fi; " \ 406 "else; " \ 407 "echo OS DOWNLOAD FAILED; " \ 408 "fi;" 409 410 #define CONFIG_PROG_OS1 \ 411 "$download_cmd $osaddr $osfile; " \ 412 "if test $? -eq 0; then " \ 413 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 414 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 415 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 416 "if test $? -ne 0; then " \ 417 "echo OS PROGRAM FAILED; " \ 418 "else; " \ 419 "echo OS PROGRAM SUCCEEDED; " \ 420 "fi; " \ 421 "else; " \ 422 "echo OS DOWNLOAD FAILED; " \ 423 "fi;" 424 425 #define CONFIG_PROG_OS2 \ 426 "$download_cmd $osaddr $osfile; " \ 427 "if test $? -eq 0; then " \ 428 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 429 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 430 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 431 "if test $? -ne 0; then " \ 432 "echo OS PROGRAM FAILED; " \ 433 "else; " \ 434 "echo OS PROGRAM SUCCEEDED; " \ 435 "fi; " \ 436 "else; " \ 437 "echo OS DOWNLOAD FAILED; " \ 438 "fi;" 439 440 #define CONFIG_PROG_FDT1 \ 441 "$download_cmd $fdtaddr $fdtfile; " \ 442 "if test $? -eq 0; then " \ 443 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 444 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 445 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 446 "if test $? -ne 0; then " \ 447 "echo FDT PROGRAM FAILED; " \ 448 "else; " \ 449 "echo FDT PROGRAM SUCCEEDED; " \ 450 "fi; " \ 451 "else; " \ 452 "echo FDT DOWNLOAD FAILED; " \ 453 "fi;" 454 455 #define CONFIG_PROG_FDT2 \ 456 "$download_cmd $fdtaddr $fdtfile; " \ 457 "if test $? -eq 0; then " \ 458 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 459 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 460 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 461 "if test $? -ne 0; then " \ 462 "echo FDT PROGRAM FAILED; " \ 463 "else; " \ 464 "echo FDT PROGRAM SUCCEEDED; " \ 465 "fi; " \ 466 "else; " \ 467 "echo FDT DOWNLOAD FAILED; " \ 468 "fi;" 469 470 #define CONFIG_EXTRA_ENV_SETTINGS \ 471 "autoload=yes\0" \ 472 "download_cmd=tftp\0" \ 473 "console_args=console=ttyS0,115200\0" \ 474 "root_args=root=/dev/nfs rw\0" \ 475 "misc_args=ip=on\0" \ 476 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 477 "bootfile=/home/user/file\0" \ 478 "osfile=/home/user/board.uImage\0" \ 479 "fdtfile=/home/user/board.dtb\0" \ 480 "ubootfile=/home/user/u-boot.bin\0" \ 481 "fdtaddr=0x1e00000\0" \ 482 "osaddr=0x1000000\0" \ 483 "loadaddr=0x1000000\0" \ 484 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 485 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 486 "prog_os1="CONFIG_PROG_OS1"\0" \ 487 "prog_os2="CONFIG_PROG_OS2"\0" \ 488 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 489 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 490 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 491 "bootcmd_flash1=run set_bootargs; " \ 492 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 493 "bootcmd_flash2=run set_bootargs; " \ 494 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 495 "bootcmd=run bootcmd_flash1\0" 496 #endif /* __CONFIG_H */ 497