1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2004-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite520x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_BOOKE		1	/* BOOKE */
18 #define CONFIG_E500		1	/* BOOKE e500 family */
19 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
20 #define CONFIG_MPC8548		1
21 #define CONFIG_XPEDITE5200	1
22 #define CONFIG_SYS_BOARD_NAME	"XPedite5200"
23 #define CONFIG_SYS_FORM_PMC_XMC	1
24 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
25 
26 #ifndef CONFIG_SYS_TEXT_BASE
27 #define CONFIG_SYS_TEXT_BASE	0xfff80000
28 #endif
29 
30 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
31 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
32 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
33 #define CONFIG_PCI1		1	/* PCI controller 1 */
34 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
35 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
36 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
37 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
38 
39 /*
40  * DDR config
41  */
42 #define CONFIG_FSL_DDR2
43 #undef CONFIG_FSL_DDR_INTERACTIVE
44 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
45 #define CONFIG_DDR_SPD
46 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
47 #define SPD_EEPROM_ADDRESS		0x54
48 #define CONFIG_NUM_DDR_CONTROLLERS	1
49 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
50 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
51 #define CONFIG_DDR_ECC
52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
53 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
54 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
55 #define CONFIG_VERY_BIG_RAM
56 
57 #define CONFIG_SYS_CLK_FREQ	66666666
58 
59 /*
60  * These can be toggled for performance analysis, otherwise use default.
61  */
62 #define CONFIG_L2_CACHE			/* toggle L2 cache */
63 #define CONFIG_BTB			/* toggle branch predition */
64 #define CONFIG_ENABLE_36BIT_PHYS	1
65 
66 #define CONFIG_SYS_CCSRBAR		0xef000000
67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
68 
69 /*
70  * Diagnostics
71  */
72 #define CONFIG_SYS_ALT_MEMTEST
73 #define CONFIG_SYS_MEMTEST_START	0x10000000
74 #define CONFIG_SYS_MEMTEST_END		0x20000000
75 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
76 					 CONFIG_SYS_POST_I2C)
77 #define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
78 					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
79 					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
80 					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
81 					 CONFIG_SYS_I2C_RTC_ADDR}
82 
83 /*
84  * Memory map
85  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
86  * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
87  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
88  * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
89  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
90  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
91  * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
92  * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
93  */
94 
95 #define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
96 
97 /*
98  * NAND flash configuration
99  */
100 #define CONFIG_SYS_NAND_BASE		0xef800000
101 #define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
102 #define CONFIG_SYS_MAX_NAND_DEVICE	1
103 #define CONFIG_NAND_ACTL
104 #define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
105 #define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
106 #define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
107 #define CONFIG_SYS_NAND_ACTL_DELAY	25
108 
109 /*
110  * NOR flash configuration
111  */
112 #define CONFIG_SYS_FLASH_BASE		0xfc000000
113 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
114 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
115 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
116 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
117 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
118 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
119 #define CONFIG_FLASH_CFI_DRIVER
120 #define CONFIG_SYS_FLASH_CFI
121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
122 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
123 						  {0xfbf40000, 0xc0000} }
124 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
125 
126 /*
127  * Chip select configuration
128  */
129 /* NOR Flash 0 on CS0 */
130 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
131 				 BR_PS_16		| \
132 				 BR_V)
133 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
134 				 OR_GPCM_ACS_DIV4	| \
135 				 OR_GPCM_SCY_8)
136 
137 /* NOR Flash 1 on CS1 */
138 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
139 				 BR_PS_16		| \
140 				 BR_V)
141 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
142 
143 /* NAND flash on CS2 */
144 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
145 				 BR_PS_8		| \
146 				 BR_V)
147 
148 /* NAND flash on CS2 */
149 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
150 				 OR_GPCM_BCTLD		| \
151 				 OR_GPCM_CSNT		| \
152 				 OR_GPCM_ACS_DIV4	| \
153 				 OR_GPCM_SCY_4		| \
154 				 OR_GPCM_TRLX		| \
155 				 OR_GPCM_EHTR)
156 
157 /* NAND flash on CS3 */
158 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
159 				 BR_PS_8		| \
160 				 BR_V)
161 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
162 
163 /*
164  * Use L1 as initial stack
165  */
166 #define CONFIG_SYS_INIT_RAM_LOCK	1
167 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
168 #define CONFIG_SYS_INIT_RAM_SIZE		0x4000
169 
170 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
171 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
172 
173 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
174 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
175 
176 /*
177  * Serial Port
178  */
179 #define CONFIG_CONS_INDEX		1
180 #define CONFIG_SYS_NS16550
181 #define CONFIG_SYS_NS16550_SERIAL
182 #define CONFIG_SYS_NS16550_REG_SIZE	1
183 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
184 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
185 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
186 #define CONFIG_SYS_BAUDRATE_TABLE	\
187 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
188 #define CONFIG_BAUDRATE			115200
189 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
190 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
191 
192 /*
193  * Use the HUSH parser
194  */
195 #define CONFIG_SYS_HUSH_PARSER
196 
197 /*
198  * Pass open firmware flat tree
199  */
200 #define CONFIG_OF_LIBFDT		1
201 #define CONFIG_OF_BOARD_SETUP		1
202 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
203 
204 /*
205  * I2C
206  */
207 #define CONFIG_SYS_I2C
208 #define CONFIG_SYS_I2C_FSL
209 #define CONFIG_SYS_FSL_I2C_SPEED	400000
210 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
211 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
212 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
213 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
214 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
215 
216 /* I2C EEPROM */
217 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
219 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
221 
222 /* I2C RTC */
223 #define CONFIG_RTC_M41T11			1
224 #define CONFIG_SYS_I2C_RTC_ADDR			0x68
225 #define CONFIG_SYS_M41T11_BASE_YEAR		2000
226 
227 /* GPIO */
228 #define CONFIG_PCA953X
229 #define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
230 #define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
231 #define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
232 
233 /* PCA957 @ 0x18 */
234 #define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
235 #define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
236 #define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
237 #define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
238 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
239 #define CONFIG_SYS_PCA953X_NVM_WP		0x20
240 #define CONFIG_SYS_PCA953X_MONARCH		0x40
241 #define CONFIG_SYS_PCA953X_EREADY		0x80
242 
243 /* PCA957 @ 0x19 */
244 #define CONFIG_SYS_PCA953X_P14_IO0		0x01
245 #define CONFIG_SYS_PCA953X_P14_IO1		0x02
246 #define CONFIG_SYS_PCA953X_P14_IO2		0x04
247 #define CONFIG_SYS_PCA953X_P14_IO3		0x08
248 #define CONFIG_SYS_PCA953X_P14_IO4		0x10
249 #define CONFIG_SYS_PCA953X_P14_IO5		0x20
250 #define CONFIG_SYS_PCA953X_P14_IO6		0x40
251 #define CONFIG_SYS_PCA953X_P14_IO7		0x80
252 
253 /* 12-bit ADC used to measure CPU diode */
254 #define CONFIG_SYS_I2C_MAX1237_ADDR		0x34
255 
256 /*
257  * General PCI
258  * Memory space is mapped 1-1, but I/O space must start from 0.
259  */
260 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
261 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
262 #define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
263 #define CONFIG_SYS_PCI1_IO_BUS		0x00000000
264 #define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
265 #define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
266 
267 /*
268  * Networking options
269  */
270 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
271 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
272 #define CONFIG_MII		1	/* MII PHY management */
273 #define CONFIG_ETHPRIME		"eTSEC1"
274 
275 #define CONFIG_TSEC1		1
276 #define CONFIG_TSEC1_NAME	"eTSEC1"
277 #define TSEC1_FLAGS		TSEC_GIGABIT
278 #define TSEC1_PHY_ADDR		1
279 #define TSEC1_PHYIDX		0
280 #define CONFIG_HAS_ETH0
281 
282 #define CONFIG_TSEC2		1
283 #define CONFIG_TSEC2_NAME	"eTSEC2"
284 #define TSEC2_FLAGS		TSEC_GIGABIT
285 #define TSEC2_PHY_ADDR		2
286 #define TSEC2_PHYIDX		0
287 #define CONFIG_HAS_ETH1
288 
289 #define CONFIG_TSEC3	1
290 #define CONFIG_TSEC3_NAME	"eTSEC3"
291 #define TSEC3_FLAGS		TSEC_GIGABIT
292 #define TSEC3_PHY_ADDR		3
293 #define TSEC3_PHYIDX		0
294 #define CONFIG_HAS_ETH2
295 
296 #define CONFIG_TSEC4	1
297 #define CONFIG_TSEC4_NAME	"eTSEC4"
298 #define TSEC4_FLAGS		TSEC_GIGABIT
299 #define TSEC4_PHY_ADDR		4
300 #define TSEC4_PHYIDX		0
301 #define CONFIG_HAS_ETH3
302 
303 /*
304  * BOOTP options
305  */
306 #define CONFIG_BOOTP_BOOTFILESIZE
307 #define CONFIG_BOOTP_BOOTPATH
308 #define CONFIG_BOOTP_GATEWAY
309 
310 /*
311  * Command configuration.
312  */
313 #include <config_cmd_default.h>
314 
315 #define CONFIG_CMD_ASKENV
316 #define CONFIG_CMD_DATE
317 #define CONFIG_CMD_DHCP
318 #define CONFIG_CMD_EEPROM
319 #define CONFIG_CMD_ELF
320 #define CONFIG_CMD_SAVEENV
321 #define CONFIG_CMD_FLASH
322 #define CONFIG_CMD_I2C
323 #define CONFIG_CMD_JFFS2
324 #define CONFIG_CMD_MII
325 #define CONFIG_CMD_NAND
326 #define CONFIG_CMD_NET
327 #define CONFIG_CMD_PCA953X
328 #define CONFIG_CMD_PCA953X_INFO
329 #define CONFIG_CMD_PCI
330 #define CONFIG_CMD_PCI_ENUM
331 #define CONFIG_CMD_PING
332 #define CONFIG_CMD_SNTP
333 #define CONFIG_CMD_REGINFO
334 
335 /*
336  * Miscellaneous configurable options
337  */
338 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
339 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
340 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
341 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
342 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
343 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
344 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
345 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
346 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
347 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
348 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
349 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
350 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
351 #define CONFIG_PREBOOT				/* enable preboot variable */
352 #define CONFIG_FIT		1
353 #define CONFIG_FIT_VERBOSE	1
354 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
355 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
356 
357 /*
358  * For booting Linux, the board info and command line data
359  * have to be in the first 16 MB of memory, since this is
360  * the maximum mapped by the Linux kernel during initialization.
361  */
362 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
363 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
364 
365 /*
366  * Environment Configuration
367  */
368 #define CONFIG_ENV_IS_IN_FLASH	1
369 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
370 #define CONFIG_ENV_SIZE		0x8000
371 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
372 
373 /*
374  * Flash memory map:
375  * fff80000 - ffffffff     Pri U-Boot (512 KB)
376  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
377  * fff00000 - fff3ffff     Pri FDT (256KB)
378  * fef00000 - ffefffff     Pri OS image (16MB)
379  * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
380  *
381  * fbf80000 - fbffffff     Sec U-Boot (512 KB)
382  * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
383  * fbf00000 - fbf3ffff     Sec FDT (256KB)
384  * faf00000 - fbefffff     Sec OS image (16MB)
385  * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
386  */
387 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
388 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xfbf80000)
389 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
390 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xfbf00000)
391 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
392 #define CONFIG_OS2_ENV_ADDR	__stringify(0xfaf00000)
393 
394 #define CONFIG_PROG_UBOOT1						\
395 	"$download_cmd $loadaddr $ubootfile; "				\
396 	"if test $? -eq 0; then "					\
397 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
398 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
399 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
400 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
401 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
402 		"if test $? -ne 0; then "				\
403 			"echo PROGRAM FAILED; "				\
404 		"else; "						\
405 			"echo PROGRAM SUCCEEDED; "			\
406 		"fi; "							\
407 	"else; "							\
408 		"echo DOWNLOAD FAILED; "				\
409 	"fi;"
410 
411 #define CONFIG_PROG_UBOOT2						\
412 	"$download_cmd $loadaddr $ubootfile; "				\
413 	"if test $? -eq 0; then "					\
414 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
415 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
416 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
417 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
418 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
419 		"if test $? -ne 0; then "				\
420 			"echo PROGRAM FAILED; "				\
421 		"else; "						\
422 			"echo PROGRAM SUCCEEDED; "			\
423 		"fi; "							\
424 	"else; "							\
425 		"echo DOWNLOAD FAILED; "				\
426 	"fi;"
427 
428 #define CONFIG_BOOT_OS_NET						\
429 	"$download_cmd $osaddr $osfile; "				\
430 	"if test $? -eq 0; then "					\
431 		"if test -n $fdtaddr; then "				\
432 			"$download_cmd $fdtaddr $fdtfile; "		\
433 			"if test $? -eq 0; then "			\
434 				"bootm $osaddr - $fdtaddr; "		\
435 			"else; "					\
436 				"echo FDT DOWNLOAD FAILED; "		\
437 			"fi; "						\
438 		"else; "						\
439 			"bootm $osaddr; "				\
440 		"fi; "							\
441 	"else; "							\
442 		"echo OS DOWNLOAD FAILED; "				\
443 	"fi;"
444 
445 #define CONFIG_PROG_OS1							\
446 	"$download_cmd $osaddr $osfile; "				\
447 	"if test $? -eq 0; then "					\
448 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
449 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
450 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
451 		"if test $? -ne 0; then "				\
452 			"echo OS PROGRAM FAILED; "			\
453 		"else; "						\
454 			"echo OS PROGRAM SUCCEEDED; "			\
455 		"fi; "							\
456 	"else; "							\
457 		"echo OS DOWNLOAD FAILED; "				\
458 	"fi;"
459 
460 #define CONFIG_PROG_OS2							\
461 	"$download_cmd $osaddr $osfile; "				\
462 	"if test $? -eq 0; then "					\
463 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
464 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
465 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
466 		"if test $? -ne 0; then "				\
467 			"echo OS PROGRAM FAILED; "			\
468 		"else; "						\
469 			"echo OS PROGRAM SUCCEEDED; "			\
470 		"fi; "							\
471 	"else; "							\
472 		"echo OS DOWNLOAD FAILED; "				\
473 	"fi;"
474 
475 #define CONFIG_PROG_FDT1						\
476 	"$download_cmd $fdtaddr $fdtfile; "				\
477 	"if test $? -eq 0; then "					\
478 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
479 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
480 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
481 		"if test $? -ne 0; then "				\
482 			"echo FDT PROGRAM FAILED; "			\
483 		"else; "						\
484 			"echo FDT PROGRAM SUCCEEDED; "			\
485 		"fi; "							\
486 	"else; "							\
487 		"echo FDT DOWNLOAD FAILED; "				\
488 	"fi;"
489 
490 #define CONFIG_PROG_FDT2						\
491 	"$download_cmd $fdtaddr $fdtfile; "				\
492 	"if test $? -eq 0; then "					\
493 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
494 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
495 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
496 		"if test $? -ne 0; then "				\
497 			"echo FDT PROGRAM FAILED; "			\
498 		"else; "						\
499 			"echo FDT PROGRAM SUCCEEDED; "			\
500 		"fi; "							\
501 	"else; "							\
502 		"echo FDT DOWNLOAD FAILED; "				\
503 	"fi;"
504 
505 #define	CONFIG_EXTRA_ENV_SETTINGS					\
506 	"autoload=yes\0"						\
507 	"download_cmd=tftp\0"						\
508 	"console_args=console=ttyS0,115200\0"				\
509 	"root_args=root=/dev/nfs rw\0"					\
510 	"misc_args=ip=on\0"						\
511 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
512 	"bootfile=/home/user/file\0"					\
513 	"osfile=/home/user/board.uImage\0"				\
514 	"fdtfile=/home/user/board.dtb\0"				\
515 	"ubootfile=/home/user/u-boot.bin\0"				\
516 	"fdtaddr=c00000\0"						\
517 	"osaddr=0x1000000\0"						\
518 	"loadaddr=0x1000000\0"						\
519 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
520 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
521 	"prog_os1="CONFIG_PROG_OS1"\0"					\
522 	"prog_os2="CONFIG_PROG_OS2"\0"					\
523 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
524 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
525 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
526 	"bootcmd_flash1=run set_bootargs; "				\
527 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
528 	"bootcmd_flash2=run set_bootargs; "				\
529 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
530 	"bootcmd=run bootcmd_flash1\0"
531 #endif	/* __CONFIG_H */
532