1 /*
2  * Copyright 2009 Extreme Engineering Solutions, Inc.
3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 /*
9  * xpedite517x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_MPC8641		1	/* MPC8641 specific */
18 #define CONFIG_XPEDITE5140	1	/* MPC8641HPCN board specific */
19 #define CONFIG_SYS_BOARD_NAME	"XPedite5170"
20 #define CONFIG_SYS_FORM_3U_VPX	1
21 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
22 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
23 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
24 #define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
25 #define CONFIG_ALTIVEC		1
26 #define CONFIG_DISPLAY_BOARDINFO
27 
28 #define	CONFIG_SYS_TEXT_BASE	0xfff00000
29 
30 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
31 #define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
32 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
33 #define CONFIG_PCIE1		1	/* PCIE controller 1 */
34 #define CONFIG_PCIE2		1	/* PCIE controller 2 */
35 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
36 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
37 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
38 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
39 
40 /*
41  * DDR config
42  */
43 #define CONFIG_SYS_FSL_DDR2
44 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
45 #define CONFIG_DDR_SPD
46 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
47 #define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
48 #define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
49 #define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
50 #define CONFIG_NUM_DDR_CONTROLLERS	2
51 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
52 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
53 #define CONFIG_DDR_ECC
54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
55 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
56 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
57 #define CONFIG_VERY_BIG_RAM
58 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
59 
60 /*
61  * virtual address to be used for temporary mappings.  There
62  * should be 128k free at this VA.
63  */
64 #define CONFIG_SYS_SCRATCH_VA	0xe0000000
65 
66 #ifndef __ASSEMBLY__
67 extern unsigned long get_board_sys_clk(unsigned long dummy);
68 #endif
69 
70 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC86xx */
71 
72 /*
73  * L2CR setup
74  */
75 #define CONFIG_SYS_L2
76 #define L2_INIT		0
77 #define L2_ENABLE	(L2CR_L2E)
78 
79 /*
80  * Base addresses -- Note these are effective addresses where the
81  * actual resources get mapped (not physical addresses)
82  */
83 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
84 #define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
85 #define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR
86 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
87 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
88 #define CONFIG_SYS_IMMR			CONFIG_SYS_CCSRBAR
89 
90 /*
91  * Diagnostics
92  */
93 #define CONFIG_SYS_ALT_MEMTEST
94 #define CONFIG_SYS_MEMTEST_START	0x10000000
95 #define CONFIG_SYS_MEMTEST_END		0x20000000
96 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY |\
97 					 CONFIG_SYS_POST_I2C)
98 #define I2C_ADDR_LIST			{CONFIG_SYS_I2C_DS1621_ADDR,	\
99 					 CONFIG_SYS_I2C_DS4510_ADDR,	\
100 					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
101 					 CONFIG_SYS_I2C_LM90_ADDR,	\
102 					 CONFIG_SYS_I2C_PCA9553_ADDR,	\
103 					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
104 					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
105 					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
106 					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
107 					 CONFIG_SYS_I2C_PEX8518_ADDR,	\
108 					 CONFIG_SYS_I2C_RTC_ADDR}
109 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
110 #define I2C_ADDR_IGNORE_LIST		{0x50}
111 
112 /*
113  * Memory map
114  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
115  * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
116  * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
117  * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
118  * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
119  * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
120  * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
121  * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
122  * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
123  * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
124  */
125 
126 #define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_4 | LCRR_EADC_3)
127 
128 /*
129  * NAND flash configuration
130  */
131 #define CONFIG_SYS_NAND_BASE		0xef800000
132 #define CONFIG_SYS_NAND_BASE2		0xef840000	/* Unused at this time */
133 #define CONFIG_SYS_NAND_BASE_LIST 	{CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
134 #define CONFIG_SYS_MAX_NAND_DEVICE	2
135 #define CONFIG_NAND_ACTL
136 #define CONFIG_SYS_NAND_ACTL_ALE 	(1 << 14)	/* C_LA14 */
137 #define CONFIG_SYS_NAND_ACTL_CLE 	(1 << 15)	/* C_LA15 */
138 #define CONFIG_SYS_NAND_ACTL_NCE	0		/* NCE not controlled by ADDR */
139 #define CONFIG_SYS_NAND_ACTL_DELAY	25
140 #define CONFIG_JFFS2_NAND
141 
142 /*
143  * NOR flash configuration
144  */
145 #define CONFIG_SYS_FLASH_BASE		0xf8000000
146 #define CONFIG_SYS_FLASH_BASE2		0xf0000000
147 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
148 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
149 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
150 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
151 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
152 #define CONFIG_FLASH_CFI_DRIVER
153 #define CONFIG_SYS_FLASH_CFI
154 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
155 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff00000, 0xc0000}, \
156 						  {0xf7f00000, 0xc0000} }
157 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
158 #define CONFIG_SYS_MONITOR_BASE_EARLY	0xfff00000	/* early monitor loc */
159 
160 /*
161  * Chip select configuration
162  */
163 /* NOR Flash 0 on CS0 */
164 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	|\
165 				 BR_PS_16		|\
166 				 BR_V)
167 #define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		|\
168 				 OR_GPCM_CSNT		|\
169 				 OR_GPCM_XACS		|\
170 				 OR_GPCM_ACS_DIV2	|\
171 				 OR_GPCM_SCY_8		|\
172 				 OR_GPCM_TRLX		|\
173 				 OR_GPCM_EHTR		|\
174 				 OR_GPCM_EAD)
175 
176 /* NOR Flash 1 on CS1 */
177 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	|\
178 				 BR_PS_16		|\
179 				 BR_V)
180 #define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
181 
182 /* NAND flash on CS2 */
183 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	|\
184 				 BR_PS_8		|\
185 				 BR_V)
186 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		|\
187 				 OR_GPCM_BCTLD		|\
188 				 OR_GPCM_CSNT		|\
189 				 OR_GPCM_ACS_DIV4	|\
190 				 OR_GPCM_SCY_4		|\
191 				 OR_GPCM_TRLX		|\
192 				 OR_GPCM_EHTR)
193 
194 /* Optional NAND flash on CS3 */
195 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	|\
196 				 BR_PS_8		|\
197 				 BR_V)
198 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
199 
200 /*
201  * Use L1 as initial stack
202  */
203 #define CONFIG_SYS_INIT_RAM_LOCK	1
204 #define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
205 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
206 
207 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
208 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
209 
210 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
211 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
212 
213 /*
214  * Serial Port
215  */
216 #define CONFIG_CONS_INDEX		1
217 #define CONFIG_SYS_NS16550_SERIAL
218 #define CONFIG_SYS_NS16550_REG_SIZE	1
219 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
220 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
221 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
222 #define CONFIG_SYS_BAUDRATE_TABLE	\
223 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
224 #define CONFIG_BAUDRATE			115200
225 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
226 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
227 
228 /*
229  * I2C
230  */
231 #define CONFIG_SYS_I2C
232 #define CONFIG_SYS_I2C_FSL
233 #define CONFIG_SYS_FSL_I2C_SPEED	100000
234 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
235 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
236 #define CONFIG_SYS_FSL_I2C2_SPEED	100000
237 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
238 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
239 
240 /* PEX8518 slave I2C interface */
241 #define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
242 
243 /* I2C DS1631 temperature sensor */
244 #define CONFIG_SYS_I2C_DS1621_ADDR	0x48
245 #define CONFIG_DTT_DS1621
246 #define CONFIG_DTT_SENSORS		{ 0 }
247 #define CONFIG_SYS_I2C_LM90_ADDR	0x4c
248 
249 /* I2C EEPROM - AT24C128B */
250 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
254 
255 /* I2C RTC */
256 #define CONFIG_RTC_M41T11		1
257 #define CONFIG_SYS_I2C_RTC_ADDR		0x68
258 #define CONFIG_SYS_M41T11_BASE_YEAR	2000
259 
260 /* GPIO/EEPROM/SRAM */
261 #define CONFIG_DS4510
262 #define CONFIG_SYS_I2C_DS4510_ADDR	0x51
263 
264 /* GPIO */
265 #define CONFIG_PCA953X
266 #define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
267 #define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
268 #define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
269 #define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
270 #define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
271 #define CONFIG_SYS_I2C_PCA9553_ADDR	0x62
272 
273 /*
274  * PU = pulled high, PD = pulled low
275  * I = input, O = output, IO = input/output
276  */
277 /* PCA9557 @ 0x18*/
278 #define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
279 #define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
280 #define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
281 #define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
282 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
283 #define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
284 
285 /* PCA9557 @ 0x1c*/
286 #define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
287 #define CONFIG_SYS_PCA953X_PLUG_GPIO0		0x02 /* Samtec connector GPIO */
288 #define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
289 #define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
290 #define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
291 #define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
292 #define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
293 #define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
294 
295 /* PCA9557 @ 0x1e*/
296 #define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
297 #define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
298 #define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
299 #define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
300 #define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
301 #define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; VPX Geographical address parity */
302 #define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; VPX P1 SYSCON */
303 
304 /* PCA9557 @ 0x1f */
305 #define CONFIG_SYS_PCA953X_VPX_GPIO0		0x01 /* PU; VPX P15 GPIO */
306 #define CONFIG_SYS_PCA953X_VPX_GPIO1		0x02 /* PU; VPX P15 GPIO */
307 #define CONFIG_SYS_PCA953X_VPX_GPIO2		0x04 /* PU; VPX P15 GPIO */
308 #define CONFIG_SYS_PCA953X_VPX_GPIO3		0x08 /* PU; VPX P15 GPIO */
309 
310 /*
311  * General PCI
312  * Memory space is mapped 1-1, but I/O space must start from 0.
313  */
314 /* PCIE1 - PEX8518 */
315 #define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
316 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
317 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
318 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
319 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
320 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
321 
322 /* PCIE2 - VPX P1 */
323 #define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
324 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
325 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
326 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
327 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
328 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
329 
330 /*
331  * Networking options
332  */
333 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
334 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
335 #define CONFIG_MII		1	/* MII PHY management */
336 #define CONFIG_ETHPRIME		"eTSEC1"
337 
338 #define CONFIG_TSEC1		1
339 #define CONFIG_TSEC1_NAME	"eTSEC1"
340 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
341 #define TSEC1_PHY_ADDR		1
342 #define TSEC1_PHYIDX		0
343 #define CONFIG_HAS_ETH0
344 
345 #define CONFIG_TSEC2		1
346 #define CONFIG_TSEC2_NAME	"eTSEC2"
347 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
348 #define TSEC2_PHY_ADDR		2
349 #define TSEC2_PHYIDX		0
350 #define CONFIG_HAS_ETH1
351 
352 /*
353  * BAT mappings
354  */
355 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
356 #define CONFIG_SYS_CCSR_DEFAULT_DBATL	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
357 					 BATL_PP_RW			|\
358 					 BATL_CACHEINHIBIT		|\
359 					 BATL_GUARDEDSTORAGE)
360 #define CONFIG_SYS_CCSR_DEFAULT_DBATU	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
361 					 BATU_BL_1M			|\
362 					 BATU_VS			|\
363 					 BATU_VP)
364 #define CONFIG_SYS_CCSR_DEFAULT_IBATL	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
365 					 BATL_PP_RW			|\
366 					 BATL_CACHEINHIBIT)
367 #define CONFIG_SYS_CCSR_DEFAULT_IBATU	CONFIG_SYS_CCSR_DEFAULT_DBATU
368 #endif
369 
370 /*
371  * BAT0		2G	Cacheable, non-guarded
372  * 0x0000_0000	2G	DDR
373  */
374 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
375 #define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
376 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
377 #define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
378 
379 /*
380  * BAT1		1G	Cache-inhibited, guarded
381  * 0x8000_0000	1G	PCI-Express 1 Memory
382  */
383 #define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
384 				 BATL_PP_RW			|\
385 				 BATL_CACHEINHIBIT		|\
386 				 BATL_GUARDEDSTORAGE)
387 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
388 				 BATU_BL_1G			|\
389 				 BATU_VS			|\
390 				 BATU_VP)
391 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
392 				 BATL_PP_RW			|\
393 				 BATL_CACHEINHIBIT)
394 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
395 
396 /*
397  * BAT2		512M	Cache-inhibited, guarded
398  * 0xc000_0000	512M	PCI-Express 2 Memory
399  */
400 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
401 				 BATL_PP_RW			|\
402 				 BATL_CACHEINHIBIT		|\
403 				 BATL_GUARDEDSTORAGE)
404 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
405 				 BATU_BL_512M			|\
406 				 BATU_VS			|\
407 				 BATU_VP)
408 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
409 				 BATL_PP_RW			|\
410 				 BATL_CACHEINHIBIT)
411 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
412 
413 /*
414  * BAT3		1M	Cache-inhibited, guarded
415  * 0xe000_0000	1M	CCSR
416  */
417 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR		|\
418 				 BATL_PP_RW			|\
419 				 BATL_CACHEINHIBIT		|\
420 				 BATL_GUARDEDSTORAGE)
421 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR		|\
422 				 BATU_BL_1M			|\
423 				 BATU_VS			|\
424 				 BATU_VP)
425 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR		|\
426 				 BATL_PP_RW			|\
427 				 BATL_CACHEINHIBIT)
428 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
429 
430 /*
431  * BAT4		32M	Cache-inhibited, guarded
432  * 0xe200_0000	16M	PCI-Express 1 I/O
433  * 0xe300_0000	16M	PCI-Express 2 I/0
434  */
435 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS	|\
436 				 BATL_PP_RW			|\
437 				 BATL_CACHEINHIBIT		|\
438 				 BATL_GUARDEDSTORAGE)
439 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_PHYS	|\
440 				 BATU_BL_32M			|\
441 				 BATU_VS			|\
442 				 BATU_VP)
443 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS	|\
444 				 BATL_PP_RW			|\
445 				 BATL_CACHEINHIBIT)
446 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
447 
448 /*
449  * BAT5		128K	Cacheable, non-guarded
450  * 0xe400_1000	128K	Init RAM for stack in the CPU DCache (no backing memory)
451  */
452 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR	|\
453 				 BATL_PP_RW			|\
454 				 BATL_MEMCOHERENCE)
455 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR	|\
456 				 BATU_BL_128K			|\
457 				 BATU_VS			|\
458 				 BATU_VP)
459 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
460 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
461 
462 /*
463  * BAT6		256M	Cache-inhibited, guarded
464  * 0xf000_0000	256M	FLASH
465  */
466 #define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE2		|\
467 				 BATL_PP_RW			|\
468 				 BATL_CACHEINHIBIT		|\
469 				 BATL_GUARDEDSTORAGE)
470 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE		|\
471 				 BATU_BL_256M			|\
472 				 BATU_VS			|\
473 				 BATU_VP)
474 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE		|\
475 				 BATL_PP_RW			|\
476 				 BATL_MEMCOHERENCE)
477 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
478 
479 /* Map the last 1M of flash where we're running from reset */
480 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY	|\
481 				 BATL_PP_RW			|\
482 				 BATL_CACHEINHIBIT		|\
483 				 BATL_GUARDEDSTORAGE)
484 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE			|\
485 				 BATU_BL_1M			|\
486 				 BATU_VS			|\
487 				 BATU_VP)
488 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY	|\
489 				 BATL_PP_RW			|\
490 				 BATL_MEMCOHERENCE)
491 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
492 
493 /*
494  * BAT7		64M	Cache-inhibited, guarded
495  * 0xe800_0000	64K	NAND FLASH
496  * 0xe804_0000	128K	DUART Registers
497  */
498 #define CONFIG_SYS_DBAT7L	(CONFIG_SYS_NAND_BASE		|\
499 				 BATL_PP_RW			|\
500 				 BATL_CACHEINHIBIT		|\
501 				 BATL_GUARDEDSTORAGE)
502 #define CONFIG_SYS_DBAT7U 	(CONFIG_SYS_NAND_BASE		|\
503 				 BATU_BL_512K			|\
504 				 BATU_VS			|\
505 				 BATU_VP)
506 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_NAND_BASE		|\
507 				 BATL_PP_RW			|\
508 				 BATL_CACHEINHIBIT)
509 #define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
510 
511 /*
512  * Command configuration.
513  */
514 #define CONFIG_CMD_DATE
515 #define CONFIG_CMD_DS4510
516 #define CONFIG_CMD_DS4510_INFO
517 #define CONFIG_CMD_DTT
518 #define CONFIG_CMD_EEPROM
519 #define CONFIG_CMD_IRQ
520 #define CONFIG_CMD_JFFS2
521 #define CONFIG_CMD_NAND
522 #define CONFIG_CMD_PCA953X
523 #define CONFIG_CMD_PCA953X_INFO
524 #define CONFIG_CMD_PCI
525 #define CONFIG_CMD_PCI_ENUM
526 #define CONFIG_CMD_REGINFO
527 
528 /*
529  * Miscellaneous configurable options
530  */
531 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
532 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
533 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
534 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
535 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
536 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
537 #define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
538 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
539 #define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
540 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
541 #define CONFIG_PREBOOT				/* enable preboot variable */
542 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
543 
544 /*
545  * For booting Linux, the board info and command line data
546  * have to be in the first 16 MB of memory, since this is
547  * the maximum mapped by the Linux kernel during initialization.
548  */
549 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
550 #define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
551 
552 /*
553  * Environment Configuration
554  */
555 #define CONFIG_ENV_IS_IN_FLASH	1
556 #define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
557 #define CONFIG_ENV_SIZE		0x8000
558 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
559 
560 /*
561  * Flash memory map:
562  * fffc0000 - ffffffff	Pri FDT (256KB)
563  * fff80000 - fffbffff	Pri U-Boot Environment (256 KB)
564  * fff00000 - fff7ffff	Pri U-Boot (512 KB)
565  * fef00000 - ffefffff	Pri OS image (16MB)
566  * f8000000 - feefffff	Pri OS Use/Filesystem (111MB)
567  *
568  * f7fc0000 - f7ffffff	Sec FDT (256KB)
569  * f7f80000 - f7fbffff	Sec U-Boot Environment (256 KB)
570  * f7f00000 - f7f7ffff	Sec U-Boot (512 KB)
571  * f6f00000 - f7efffff	Sec OS image (16MB)
572  * f0000000 - f6efffff	Sec OS Use/Filesystem (111MB)
573  */
574 #define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff00000)
575 #define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f00000)
576 #define CONFIG_FDT1_ENV_ADDR	__stringify(0xfffc0000)
577 #define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7fc0000)
578 #define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
579 #define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
580 
581 #define CONFIG_PROG_UBOOT1						\
582 	"$download_cmd $loadaddr $ubootfile; "				\
583 	"if test $? -eq 0; then "					\
584 		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
585 		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
586 		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
587 		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
588 		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
589 		"if test $? -ne 0; then "				\
590 			"echo PROGRAM FAILED; "				\
591 		"else; "						\
592 			"echo PROGRAM SUCCEEDED; "			\
593 		"fi; "							\
594 	"else; "							\
595 		"echo DOWNLOAD FAILED; "				\
596 	"fi;"
597 
598 #define CONFIG_PROG_UBOOT2						\
599 	"$download_cmd $loadaddr $ubootfile; "				\
600 	"if test $? -eq 0; then "					\
601 		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
602 		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
603 		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
604 		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
605 		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
606 		"if test $? -ne 0; then "				\
607 			"echo PROGRAM FAILED; "				\
608 		"else; "						\
609 			"echo PROGRAM SUCCEEDED; "			\
610 		"fi; "							\
611 	"else; "							\
612 		"echo DOWNLOAD FAILED; "				\
613 	"fi;"
614 
615 #define CONFIG_BOOT_OS_NET						\
616 	"$download_cmd $osaddr $osfile; "				\
617 	"if test $? -eq 0; then "					\
618 		"if test -n $fdtaddr; then "				\
619 			"$download_cmd $fdtaddr $fdtfile; "		\
620 			"if test $? -eq 0; then "			\
621 				"bootm $osaddr - $fdtaddr; "		\
622 			"else; "					\
623 				"echo FDT DOWNLOAD FAILED; "		\
624 			"fi; "						\
625 		"else; "						\
626 			"bootm $osaddr; "				\
627 		"fi; "							\
628 	"else; "							\
629 		"echo OS DOWNLOAD FAILED; "				\
630 	"fi;"
631 
632 #define CONFIG_PROG_OS1							\
633 	"$download_cmd $osaddr $osfile; "				\
634 	"if test $? -eq 0; then "					\
635 		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
636 		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
637 		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
638 		"if test $? -ne 0; then "				\
639 			"echo OS PROGRAM FAILED; "			\
640 		"else; "						\
641 			"echo OS PROGRAM SUCCEEDED; "			\
642 		"fi; "							\
643 	"else; "							\
644 		"echo OS DOWNLOAD FAILED; "				\
645 	"fi;"
646 
647 #define CONFIG_PROG_OS2							\
648 	"$download_cmd $osaddr $osfile; "				\
649 	"if test $? -eq 0; then "					\
650 		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
651 		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
652 		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
653 		"if test $? -ne 0; then "				\
654 			"echo OS PROGRAM FAILED; "			\
655 		"else; "						\
656 			"echo OS PROGRAM SUCCEEDED; "			\
657 		"fi; "							\
658 	"else; "							\
659 		"echo OS DOWNLOAD FAILED; "				\
660 	"fi;"
661 
662 #define CONFIG_PROG_FDT1						\
663 	"$download_cmd $fdtaddr $fdtfile; "				\
664 	"if test $? -eq 0; then "					\
665 		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
666 		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
667 		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
668 		"if test $? -ne 0; then "				\
669 			"echo FDT PROGRAM FAILED; "			\
670 		"else; "						\
671 			"echo FDT PROGRAM SUCCEEDED; "			\
672 		"fi; "							\
673 	"else; "							\
674 		"echo FDT DOWNLOAD FAILED; "				\
675 	"fi;"
676 
677 #define CONFIG_PROG_FDT2						\
678 	"$download_cmd $fdtaddr $fdtfile; "				\
679 	"if test $? -eq 0; then "					\
680 		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
681 		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
682 		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
683 		"if test $? -ne 0; then "				\
684 			"echo FDT PROGRAM FAILED; "			\
685 		"else; "						\
686 			"echo FDT PROGRAM SUCCEEDED; "			\
687 		"fi; "							\
688 	"else; "							\
689 		"echo FDT DOWNLOAD FAILED; "				\
690 	"fi;"
691 
692 #define	CONFIG_EXTRA_ENV_SETTINGS					\
693 	"autoload=yes\0"						\
694 	"download_cmd=tftp\0"						\
695 	"console_args=console=ttyS0,115200\0"				\
696 	"root_args=root=/dev/nfs rw\0"					\
697 	"misc_args=ip=on\0"						\
698 	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
699 	"bootfile=/home/user/file\0"					\
700 	"osfile=/home/user/board.uImage\0"				\
701 	"fdtfile=/home/user/board.dtb\0"				\
702 	"ubootfile=/home/user/u-boot.bin\0"				\
703 	"fdtaddr=c00000\0"						\
704 	"osaddr=0x1000000\0"						\
705 	"loadaddr=0x1000000\0"						\
706 	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
707 	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
708 	"prog_os1="CONFIG_PROG_OS1"\0"					\
709 	"prog_os2="CONFIG_PROG_OS2"\0"					\
710 	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
711 	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
712 	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
713 	"bootcmd_flash1=run set_bootargs; "				\
714 		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
715 	"bootcmd_flash2=run set_bootargs; "				\
716 		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
717 	"bootcmd=run bootcmd_flash1\0"
718 #endif	/* __CONFIG_H */
719