1 /* 2 * Copyright 2009 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite517x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 18 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ 19 #define CONFIG_SYS_BOARD_NAME "XPedite5170" 20 #define CONFIG_SYS_FORM_3U_VPX 1 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 23 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 24 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 25 #define CONFIG_ALTIVEC 1 26 27 #define CONFIG_SYS_TEXT_BASE 0xfff00000 28 29 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 30 #define CONFIG_PCIE1 1 /* PCIE controller 1 */ 31 #define CONFIG_PCIE2 1 /* PCIE controller 2 */ 32 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 33 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 34 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 35 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 36 37 /* 38 * DDR config 39 */ 40 #define CONFIG_SYS_FSL_DDR2 41 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 42 #define CONFIG_DDR_SPD 43 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 44 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 45 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 46 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 47 #define CONFIG_NUM_DDR_CONTROLLERS 2 48 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 49 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 50 #define CONFIG_DDR_ECC 51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 53 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 54 #define CONFIG_VERY_BIG_RAM 55 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 56 57 /* 58 * virtual address to be used for temporary mappings. There 59 * should be 128k free at this VA. 60 */ 61 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 62 63 #ifndef __ASSEMBLY__ 64 extern unsigned long get_board_sys_clk(unsigned long dummy); 65 #endif 66 67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ 68 69 /* 70 * L2CR setup 71 */ 72 #define CONFIG_SYS_L2 73 #define L2_INIT 0 74 #define L2_ENABLE (L2CR_L2E) 75 76 /* 77 * Base addresses -- Note these are effective addresses where the 78 * actual resources get mapped (not physical addresses) 79 */ 80 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 81 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ 82 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 83 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 84 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 85 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 86 87 /* 88 * Diagnostics 89 */ 90 #define CONFIG_SYS_ALT_MEMTEST 91 #define CONFIG_SYS_MEMTEST_START 0x10000000 92 #define CONFIG_SYS_MEMTEST_END 0x20000000 93 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\ 94 CONFIG_SYS_POST_I2C) 95 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \ 96 CONFIG_SYS_I2C_DS4510_ADDR, \ 97 CONFIG_SYS_I2C_EEPROM_ADDR, \ 98 CONFIG_SYS_I2C_LM90_ADDR, \ 99 CONFIG_SYS_I2C_PCA9553_ADDR, \ 100 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 101 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 102 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 103 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 104 CONFIG_SYS_I2C_PEX8518_ADDR, \ 105 CONFIG_SYS_I2C_RTC_ADDR} 106 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */ 107 #define I2C_ADDR_IGNORE_LIST {0x50} 108 109 /* 110 * Memory map 111 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 112 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 113 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 114 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 115 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 116 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 117 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 118 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 119 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 120 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 121 */ 122 123 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) 124 125 /* 126 * NAND flash configuration 127 */ 128 #define CONFIG_SYS_NAND_BASE 0xef800000 129 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 130 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} 131 #define CONFIG_SYS_MAX_NAND_DEVICE 2 132 #define CONFIG_NAND_ACTL 133 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ 134 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ 135 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ 136 #define CONFIG_SYS_NAND_ACTL_DELAY 25 137 #define CONFIG_JFFS2_NAND 138 139 /* 140 * NOR flash configuration 141 */ 142 #define CONFIG_SYS_FLASH_BASE 0xf8000000 143 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 144 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 145 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 146 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 147 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 148 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 149 #define CONFIG_FLASH_CFI_DRIVER 150 #define CONFIG_SYS_FLASH_CFI 151 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 152 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ 153 {0xf7f00000, 0xc0000} } 154 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 155 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 156 157 /* 158 * Chip select configuration 159 */ 160 /* NOR Flash 0 on CS0 */ 161 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ 162 BR_PS_16 |\ 163 BR_V) 164 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ 165 OR_GPCM_CSNT |\ 166 OR_GPCM_XACS |\ 167 OR_GPCM_ACS_DIV2 |\ 168 OR_GPCM_SCY_8 |\ 169 OR_GPCM_TRLX |\ 170 OR_GPCM_EHTR |\ 171 OR_GPCM_EAD) 172 173 /* NOR Flash 1 on CS1 */ 174 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ 175 BR_PS_16 |\ 176 BR_V) 177 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 178 179 /* NAND flash on CS2 */ 180 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ 181 BR_PS_8 |\ 182 BR_V) 183 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ 184 OR_GPCM_BCTLD |\ 185 OR_GPCM_CSNT |\ 186 OR_GPCM_ACS_DIV4 |\ 187 OR_GPCM_SCY_4 |\ 188 OR_GPCM_TRLX |\ 189 OR_GPCM_EHTR) 190 191 /* Optional NAND flash on CS3 */ 192 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ 193 BR_PS_8 |\ 194 BR_V) 195 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 196 197 /* 198 * Use L1 as initial stack 199 */ 200 #define CONFIG_SYS_INIT_RAM_LOCK 1 201 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 202 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 203 204 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 205 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 206 207 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 208 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 209 210 /* 211 * Serial Port 212 */ 213 #define CONFIG_CONS_INDEX 1 214 #define CONFIG_SYS_NS16550_SERIAL 215 #define CONFIG_SYS_NS16550_REG_SIZE 1 216 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 217 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 218 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 219 #define CONFIG_SYS_BAUDRATE_TABLE \ 220 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 221 #define CONFIG_BAUDRATE 115200 222 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 223 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 224 225 /* 226 * I2C 227 */ 228 #define CONFIG_SYS_I2C 229 #define CONFIG_SYS_I2C_FSL 230 #define CONFIG_SYS_FSL_I2C_SPEED 100000 231 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 232 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 233 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 234 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 235 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 236 237 /* PEX8518 slave I2C interface */ 238 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 239 240 /* I2C DS1631 temperature sensor */ 241 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 242 #define CONFIG_DTT_DS1621 243 #define CONFIG_DTT_SENSORS { 0 } 244 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 245 246 /* I2C EEPROM - AT24C128B */ 247 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 248 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 251 252 /* I2C RTC */ 253 #define CONFIG_RTC_M41T11 1 254 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 255 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 256 257 /* GPIO/EEPROM/SRAM */ 258 #define CONFIG_DS4510 259 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 260 261 /* GPIO */ 262 #define CONFIG_PCA953X 263 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 264 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 265 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 266 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 267 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 268 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62 269 270 /* 271 * PU = pulled high, PD = pulled low 272 * I = input, O = output, IO = input/output 273 */ 274 /* PCA9557 @ 0x18*/ 275 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 276 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 277 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 278 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 279 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 280 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 281 282 /* PCA9557 @ 0x1c*/ 283 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 284 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ 285 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 286 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 287 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 288 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 289 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 290 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 291 292 /* PCA9557 @ 0x1e*/ 293 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 294 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 295 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 296 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 297 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 298 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ 299 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ 300 301 /* PCA9557 @ 0x1f */ 302 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ 303 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ 304 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ 305 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ 306 307 /* 308 * General PCI 309 * Memory space is mapped 1-1, but I/O space must start from 0. 310 */ 311 /* PCIE1 - PEX8518 */ 312 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 313 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 314 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 315 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 316 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 317 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 318 319 /* PCIE2 - VPX P1 */ 320 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 321 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 322 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 323 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 324 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 325 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 326 327 /* 328 * Networking options 329 */ 330 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 331 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 332 #define CONFIG_MII 1 /* MII PHY management */ 333 #define CONFIG_ETHPRIME "eTSEC1" 334 335 #define CONFIG_TSEC1 1 336 #define CONFIG_TSEC1_NAME "eTSEC1" 337 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 338 #define TSEC1_PHY_ADDR 1 339 #define TSEC1_PHYIDX 0 340 #define CONFIG_HAS_ETH0 341 342 #define CONFIG_TSEC2 1 343 #define CONFIG_TSEC2_NAME "eTSEC2" 344 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 345 #define TSEC2_PHY_ADDR 2 346 #define TSEC2_PHYIDX 0 347 #define CONFIG_HAS_ETH1 348 349 /* 350 * BAT mappings 351 */ 352 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 353 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ 354 BATL_PP_RW |\ 355 BATL_CACHEINHIBIT |\ 356 BATL_GUARDEDSTORAGE) 357 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ 358 BATU_BL_1M |\ 359 BATU_VS |\ 360 BATU_VP) 361 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ 362 BATL_PP_RW |\ 363 BATL_CACHEINHIBIT) 364 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 365 #endif 366 367 /* 368 * BAT0 2G Cacheable, non-guarded 369 * 0x0000_0000 2G DDR 370 */ 371 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 372 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 373 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 374 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 375 376 /* 377 * BAT1 1G Cache-inhibited, guarded 378 * 0x8000_0000 1G PCI-Express 1 Memory 379 */ 380 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ 381 BATL_PP_RW |\ 382 BATL_CACHEINHIBIT |\ 383 BATL_GUARDEDSTORAGE) 384 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ 385 BATU_BL_1G |\ 386 BATU_VS |\ 387 BATU_VP) 388 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ 389 BATL_PP_RW |\ 390 BATL_CACHEINHIBIT) 391 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 392 393 /* 394 * BAT2 512M Cache-inhibited, guarded 395 * 0xc000_0000 512M PCI-Express 2 Memory 396 */ 397 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ 398 BATL_PP_RW |\ 399 BATL_CACHEINHIBIT |\ 400 BATL_GUARDEDSTORAGE) 401 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ 402 BATU_BL_512M |\ 403 BATU_VS |\ 404 BATU_VP) 405 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ 406 BATL_PP_RW |\ 407 BATL_CACHEINHIBIT) 408 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 409 410 /* 411 * BAT3 1M Cache-inhibited, guarded 412 * 0xe000_0000 1M CCSR 413 */ 414 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ 415 BATL_PP_RW |\ 416 BATL_CACHEINHIBIT |\ 417 BATL_GUARDEDSTORAGE) 418 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ 419 BATU_BL_1M |\ 420 BATU_VS |\ 421 BATU_VP) 422 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ 423 BATL_PP_RW |\ 424 BATL_CACHEINHIBIT) 425 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 426 427 /* 428 * BAT4 32M Cache-inhibited, guarded 429 * 0xe200_0000 16M PCI-Express 1 I/O 430 * 0xe300_0000 16M PCI-Express 2 I/0 431 */ 432 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ 433 BATL_PP_RW |\ 434 BATL_CACHEINHIBIT |\ 435 BATL_GUARDEDSTORAGE) 436 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ 437 BATU_BL_32M |\ 438 BATU_VS |\ 439 BATU_VP) 440 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ 441 BATL_PP_RW |\ 442 BATL_CACHEINHIBIT) 443 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 444 445 /* 446 * BAT5 128K Cacheable, non-guarded 447 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) 448 */ 449 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ 450 BATL_PP_RW |\ 451 BATL_MEMCOHERENCE) 452 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ 453 BATU_BL_128K |\ 454 BATU_VS |\ 455 BATU_VP) 456 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 457 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 458 459 /* 460 * BAT6 256M Cache-inhibited, guarded 461 * 0xf000_0000 256M FLASH 462 */ 463 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ 464 BATL_PP_RW |\ 465 BATL_CACHEINHIBIT |\ 466 BATL_GUARDEDSTORAGE) 467 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ 468 BATU_BL_256M |\ 469 BATU_VS |\ 470 BATU_VP) 471 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ 472 BATL_PP_RW |\ 473 BATL_MEMCOHERENCE) 474 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 475 476 /* Map the last 1M of flash where we're running from reset */ 477 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ 478 BATL_PP_RW |\ 479 BATL_CACHEINHIBIT |\ 480 BATL_GUARDEDSTORAGE) 481 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\ 482 BATU_BL_1M |\ 483 BATU_VS |\ 484 BATU_VP) 485 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ 486 BATL_PP_RW |\ 487 BATL_MEMCOHERENCE) 488 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 489 490 /* 491 * BAT7 64M Cache-inhibited, guarded 492 * 0xe800_0000 64K NAND FLASH 493 * 0xe804_0000 128K DUART Registers 494 */ 495 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ 496 BATL_PP_RW |\ 497 BATL_CACHEINHIBIT |\ 498 BATL_GUARDEDSTORAGE) 499 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ 500 BATU_BL_512K |\ 501 BATU_VS |\ 502 BATU_VP) 503 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ 504 BATL_PP_RW |\ 505 BATL_CACHEINHIBIT) 506 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 507 508 /* 509 * Command configuration. 510 */ 511 #define CONFIG_CMD_DATE 512 #define CONFIG_CMD_DS4510 513 #define CONFIG_CMD_DS4510_INFO 514 #define CONFIG_CMD_DTT 515 #define CONFIG_CMD_EEPROM 516 #define CONFIG_CMD_IRQ 517 #define CONFIG_CMD_JFFS2 518 #define CONFIG_CMD_NAND 519 #define CONFIG_CMD_PCA953X 520 #define CONFIG_CMD_PCA953X_INFO 521 #define CONFIG_CMD_PCI 522 #define CONFIG_CMD_PCI_ENUM 523 #define CONFIG_CMD_REGINFO 524 525 /* 526 * Miscellaneous configurable options 527 */ 528 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 529 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 530 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 531 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 532 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 533 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 534 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ 535 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 536 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 537 #define CONFIG_PREBOOT /* enable preboot variable */ 538 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 539 540 /* 541 * For booting Linux, the board info and command line data 542 * have to be in the first 16 MB of memory, since this is 543 * the maximum mapped by the Linux kernel during initialization. 544 */ 545 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 546 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 547 548 /* 549 * Environment Configuration 550 */ 551 #define CONFIG_ENV_IS_IN_FLASH 1 552 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 553 #define CONFIG_ENV_SIZE 0x8000 554 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 555 556 /* 557 * Flash memory map: 558 * fffc0000 - ffffffff Pri FDT (256KB) 559 * fff80000 - fffbffff Pri U-Boot Environment (256 KB) 560 * fff00000 - fff7ffff Pri U-Boot (512 KB) 561 * fef00000 - ffefffff Pri OS image (16MB) 562 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 563 * 564 * f7fc0000 - f7ffffff Sec FDT (256KB) 565 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) 566 * f7f00000 - f7f7ffff Sec U-Boot (512 KB) 567 * f6f00000 - f7efffff Sec OS image (16MB) 568 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 569 */ 570 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000) 571 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000) 572 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000) 573 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000) 574 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 575 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 576 577 #define CONFIG_PROG_UBOOT1 \ 578 "$download_cmd $loadaddr $ubootfile; " \ 579 "if test $? -eq 0; then " \ 580 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 581 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 582 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 583 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 584 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 585 "if test $? -ne 0; then " \ 586 "echo PROGRAM FAILED; " \ 587 "else; " \ 588 "echo PROGRAM SUCCEEDED; " \ 589 "fi; " \ 590 "else; " \ 591 "echo DOWNLOAD FAILED; " \ 592 "fi;" 593 594 #define CONFIG_PROG_UBOOT2 \ 595 "$download_cmd $loadaddr $ubootfile; " \ 596 "if test $? -eq 0; then " \ 597 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 598 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 599 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 600 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 601 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 602 "if test $? -ne 0; then " \ 603 "echo PROGRAM FAILED; " \ 604 "else; " \ 605 "echo PROGRAM SUCCEEDED; " \ 606 "fi; " \ 607 "else; " \ 608 "echo DOWNLOAD FAILED; " \ 609 "fi;" 610 611 #define CONFIG_BOOT_OS_NET \ 612 "$download_cmd $osaddr $osfile; " \ 613 "if test $? -eq 0; then " \ 614 "if test -n $fdtaddr; then " \ 615 "$download_cmd $fdtaddr $fdtfile; " \ 616 "if test $? -eq 0; then " \ 617 "bootm $osaddr - $fdtaddr; " \ 618 "else; " \ 619 "echo FDT DOWNLOAD FAILED; " \ 620 "fi; " \ 621 "else; " \ 622 "bootm $osaddr; " \ 623 "fi; " \ 624 "else; " \ 625 "echo OS DOWNLOAD FAILED; " \ 626 "fi;" 627 628 #define CONFIG_PROG_OS1 \ 629 "$download_cmd $osaddr $osfile; " \ 630 "if test $? -eq 0; then " \ 631 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 632 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 633 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 634 "if test $? -ne 0; then " \ 635 "echo OS PROGRAM FAILED; " \ 636 "else; " \ 637 "echo OS PROGRAM SUCCEEDED; " \ 638 "fi; " \ 639 "else; " \ 640 "echo OS DOWNLOAD FAILED; " \ 641 "fi;" 642 643 #define CONFIG_PROG_OS2 \ 644 "$download_cmd $osaddr $osfile; " \ 645 "if test $? -eq 0; then " \ 646 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 647 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 648 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 649 "if test $? -ne 0; then " \ 650 "echo OS PROGRAM FAILED; " \ 651 "else; " \ 652 "echo OS PROGRAM SUCCEEDED; " \ 653 "fi; " \ 654 "else; " \ 655 "echo OS DOWNLOAD FAILED; " \ 656 "fi;" 657 658 #define CONFIG_PROG_FDT1 \ 659 "$download_cmd $fdtaddr $fdtfile; " \ 660 "if test $? -eq 0; then " \ 661 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 662 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 663 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 664 "if test $? -ne 0; then " \ 665 "echo FDT PROGRAM FAILED; " \ 666 "else; " \ 667 "echo FDT PROGRAM SUCCEEDED; " \ 668 "fi; " \ 669 "else; " \ 670 "echo FDT DOWNLOAD FAILED; " \ 671 "fi;" 672 673 #define CONFIG_PROG_FDT2 \ 674 "$download_cmd $fdtaddr $fdtfile; " \ 675 "if test $? -eq 0; then " \ 676 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 677 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 678 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 679 "if test $? -ne 0; then " \ 680 "echo FDT PROGRAM FAILED; " \ 681 "else; " \ 682 "echo FDT PROGRAM SUCCEEDED; " \ 683 "fi; " \ 684 "else; " \ 685 "echo FDT DOWNLOAD FAILED; " \ 686 "fi;" 687 688 #define CONFIG_EXTRA_ENV_SETTINGS \ 689 "autoload=yes\0" \ 690 "download_cmd=tftp\0" \ 691 "console_args=console=ttyS0,115200\0" \ 692 "root_args=root=/dev/nfs rw\0" \ 693 "misc_args=ip=on\0" \ 694 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 695 "bootfile=/home/user/file\0" \ 696 "osfile=/home/user/board.uImage\0" \ 697 "fdtfile=/home/user/board.dtb\0" \ 698 "ubootfile=/home/user/u-boot.bin\0" \ 699 "fdtaddr=0x1e00000\0" \ 700 "osaddr=0x1000000\0" \ 701 "loadaddr=0x1000000\0" \ 702 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 703 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 704 "prog_os1="CONFIG_PROG_OS1"\0" \ 705 "prog_os2="CONFIG_PROG_OS2"\0" \ 706 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 707 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 708 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 709 "bootcmd_flash1=run set_bootargs; " \ 710 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 711 "bootcmd_flash2=run set_bootargs; " \ 712 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 713 "bootcmd=run bootcmd_flash1\0" 714 #endif /* __CONFIG_H */ 715