1 /* 2 * Copyright 2009 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite517x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_SYS_BOARD_NAME "XPedite5170" 18 #define CONFIG_SYS_FORM_3U_VPX 1 19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 20 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 21 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 22 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 23 #define CONFIG_ALTIVEC 1 24 25 #define CONFIG_SYS_TEXT_BASE 0xfff00000 26 27 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 28 #define CONFIG_PCIE1 1 /* PCIE controller 1 */ 29 #define CONFIG_PCIE2 1 /* PCIE controller 2 */ 30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 33 34 /* 35 * DDR config 36 */ 37 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 38 #define CONFIG_DDR_SPD 39 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 40 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 41 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 42 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 43 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 44 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 45 #define CONFIG_DDR_ECC 46 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 47 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 48 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 49 #define CONFIG_VERY_BIG_RAM 50 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 51 52 /* 53 * virtual address to be used for temporary mappings. There 54 * should be 128k free at this VA. 55 */ 56 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 57 58 #ifndef __ASSEMBLY__ 59 extern unsigned long get_board_sys_clk(unsigned long dummy); 60 #endif 61 62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ 63 64 /* 65 * L2CR setup 66 */ 67 #define CONFIG_SYS_L2 68 #define L2_INIT 0 69 #define L2_ENABLE (L2CR_L2E) 70 71 /* 72 * Base addresses -- Note these are effective addresses where the 73 * actual resources get mapped (not physical addresses) 74 */ 75 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ 76 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 78 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 79 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 80 81 /* 82 * Diagnostics 83 */ 84 #define CONFIG_SYS_ALT_MEMTEST 85 #define CONFIG_SYS_MEMTEST_START 0x10000000 86 #define CONFIG_SYS_MEMTEST_END 0x20000000 87 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\ 88 CONFIG_SYS_POST_I2C) 89 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */ 90 #define I2C_ADDR_IGNORE_LIST {0x50} 91 92 /* 93 * Memory map 94 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 95 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 96 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 97 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 98 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 99 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 100 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 101 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 102 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 103 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 104 */ 105 106 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) 107 108 /* 109 * NAND flash configuration 110 */ 111 #define CONFIG_SYS_NAND_BASE 0xef800000 112 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 113 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} 114 #define CONFIG_SYS_MAX_NAND_DEVICE 2 115 #define CONFIG_NAND_ACTL 116 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ 117 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ 118 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ 119 #define CONFIG_SYS_NAND_ACTL_DELAY 25 120 #define CONFIG_JFFS2_NAND 121 122 /* 123 * NOR flash configuration 124 */ 125 #define CONFIG_SYS_FLASH_BASE 0xf8000000 126 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 127 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 128 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 129 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 130 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 131 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 132 #define CONFIG_FLASH_CFI_DRIVER 133 #define CONFIG_SYS_FLASH_CFI 134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 135 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ 136 {0xf7f00000, 0xc0000} } 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 138 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 139 140 /* 141 * Chip select configuration 142 */ 143 /* NOR Flash 0 on CS0 */ 144 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ 145 BR_PS_16 |\ 146 BR_V) 147 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ 148 OR_GPCM_CSNT |\ 149 OR_GPCM_XACS |\ 150 OR_GPCM_ACS_DIV2 |\ 151 OR_GPCM_SCY_8 |\ 152 OR_GPCM_TRLX |\ 153 OR_GPCM_EHTR |\ 154 OR_GPCM_EAD) 155 156 /* NOR Flash 1 on CS1 */ 157 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ 158 BR_PS_16 |\ 159 BR_V) 160 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 161 162 /* NAND flash on CS2 */ 163 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ 164 BR_PS_8 |\ 165 BR_V) 166 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ 167 OR_GPCM_BCTLD |\ 168 OR_GPCM_CSNT |\ 169 OR_GPCM_ACS_DIV4 |\ 170 OR_GPCM_SCY_4 |\ 171 OR_GPCM_TRLX |\ 172 OR_GPCM_EHTR) 173 174 /* Optional NAND flash on CS3 */ 175 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ 176 BR_PS_8 |\ 177 BR_V) 178 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 179 180 /* 181 * Use L1 as initial stack 182 */ 183 #define CONFIG_SYS_INIT_RAM_LOCK 1 184 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 185 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 186 187 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 189 190 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 191 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 192 193 /* 194 * Serial Port 195 */ 196 #define CONFIG_CONS_INDEX 1 197 #define CONFIG_SYS_NS16550_SERIAL 198 #define CONFIG_SYS_NS16550_REG_SIZE 1 199 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 200 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 201 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 202 #define CONFIG_SYS_BAUDRATE_TABLE \ 203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 204 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 205 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 206 207 /* 208 * I2C 209 */ 210 #define CONFIG_SYS_I2C 211 #define CONFIG_SYS_I2C_FSL 212 #define CONFIG_SYS_FSL_I2C_SPEED 100000 213 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 214 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 215 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 216 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 217 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 218 219 /* PEX8518 slave I2C interface */ 220 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 221 222 /* I2C DS1631 temperature sensor */ 223 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 224 225 /* I2C EEPROM - AT24C128B */ 226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 230 231 /* I2C RTC */ 232 #define CONFIG_RTC_M41T11 1 233 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 234 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 235 236 /* GPIO */ 237 #define CONFIG_PCA953X 238 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 239 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 240 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 241 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 242 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 243 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62 244 245 /* 246 * PU = pulled high, PD = pulled low 247 * I = input, O = output, IO = input/output 248 */ 249 /* PCA9557 @ 0x18*/ 250 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 251 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 252 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 253 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 254 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 255 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 256 257 /* PCA9557 @ 0x1c*/ 258 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 259 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ 260 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 261 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 262 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 263 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 264 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 265 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 266 267 /* PCA9557 @ 0x1e*/ 268 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 269 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 270 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 271 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 272 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 273 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ 274 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ 275 276 /* PCA9557 @ 0x1f */ 277 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ 278 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ 279 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ 280 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ 281 282 /* 283 * General PCI 284 * Memory space is mapped 1-1, but I/O space must start from 0. 285 */ 286 /* PCIE1 - PEX8518 */ 287 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 288 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 289 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 290 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 291 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 292 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 293 294 /* PCIE2 - VPX P1 */ 295 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 296 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 297 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 298 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 299 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 300 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 301 302 /* 303 * Networking options 304 */ 305 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 306 #define CONFIG_MII 1 /* MII PHY management */ 307 #define CONFIG_ETHPRIME "eTSEC1" 308 309 #define CONFIG_TSEC1 1 310 #define CONFIG_TSEC1_NAME "eTSEC1" 311 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 312 #define TSEC1_PHY_ADDR 1 313 #define TSEC1_PHYIDX 0 314 #define CONFIG_HAS_ETH0 315 316 #define CONFIG_TSEC2 1 317 #define CONFIG_TSEC2_NAME "eTSEC2" 318 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 319 #define TSEC2_PHY_ADDR 2 320 #define TSEC2_PHYIDX 0 321 #define CONFIG_HAS_ETH1 322 323 /* 324 * BAT mappings 325 */ 326 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 327 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ 328 BATL_PP_RW |\ 329 BATL_CACHEINHIBIT |\ 330 BATL_GUARDEDSTORAGE) 331 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ 332 BATU_BL_1M |\ 333 BATU_VS |\ 334 BATU_VP) 335 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ 336 BATL_PP_RW |\ 337 BATL_CACHEINHIBIT) 338 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 339 #endif 340 341 /* 342 * BAT0 2G Cacheable, non-guarded 343 * 0x0000_0000 2G DDR 344 */ 345 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 346 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 347 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 348 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 349 350 /* 351 * BAT1 1G Cache-inhibited, guarded 352 * 0x8000_0000 1G PCI-Express 1 Memory 353 */ 354 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ 355 BATL_PP_RW |\ 356 BATL_CACHEINHIBIT |\ 357 BATL_GUARDEDSTORAGE) 358 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ 359 BATU_BL_1G |\ 360 BATU_VS |\ 361 BATU_VP) 362 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ 363 BATL_PP_RW |\ 364 BATL_CACHEINHIBIT) 365 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 366 367 /* 368 * BAT2 512M Cache-inhibited, guarded 369 * 0xc000_0000 512M PCI-Express 2 Memory 370 */ 371 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ 372 BATL_PP_RW |\ 373 BATL_CACHEINHIBIT |\ 374 BATL_GUARDEDSTORAGE) 375 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ 376 BATU_BL_512M |\ 377 BATU_VS |\ 378 BATU_VP) 379 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ 380 BATL_PP_RW |\ 381 BATL_CACHEINHIBIT) 382 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 383 384 /* 385 * BAT3 1M Cache-inhibited, guarded 386 * 0xe000_0000 1M CCSR 387 */ 388 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ 389 BATL_PP_RW |\ 390 BATL_CACHEINHIBIT |\ 391 BATL_GUARDEDSTORAGE) 392 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ 393 BATU_BL_1M |\ 394 BATU_VS |\ 395 BATU_VP) 396 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ 397 BATL_PP_RW |\ 398 BATL_CACHEINHIBIT) 399 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 400 401 /* 402 * BAT4 32M Cache-inhibited, guarded 403 * 0xe200_0000 16M PCI-Express 1 I/O 404 * 0xe300_0000 16M PCI-Express 2 I/0 405 */ 406 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ 407 BATL_PP_RW |\ 408 BATL_CACHEINHIBIT |\ 409 BATL_GUARDEDSTORAGE) 410 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ 411 BATU_BL_32M |\ 412 BATU_VS |\ 413 BATU_VP) 414 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ 415 BATL_PP_RW |\ 416 BATL_CACHEINHIBIT) 417 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 418 419 /* 420 * BAT5 128K Cacheable, non-guarded 421 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) 422 */ 423 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ 424 BATL_PP_RW |\ 425 BATL_MEMCOHERENCE) 426 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ 427 BATU_BL_128K |\ 428 BATU_VS |\ 429 BATU_VP) 430 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 431 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 432 433 /* 434 * BAT6 256M Cache-inhibited, guarded 435 * 0xf000_0000 256M FLASH 436 */ 437 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ 438 BATL_PP_RW |\ 439 BATL_CACHEINHIBIT |\ 440 BATL_GUARDEDSTORAGE) 441 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ 442 BATU_BL_256M |\ 443 BATU_VS |\ 444 BATU_VP) 445 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ 446 BATL_PP_RW |\ 447 BATL_MEMCOHERENCE) 448 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 449 450 /* Map the last 1M of flash where we're running from reset */ 451 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ 452 BATL_PP_RW |\ 453 BATL_CACHEINHIBIT |\ 454 BATL_GUARDEDSTORAGE) 455 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\ 456 BATU_BL_1M |\ 457 BATU_VS |\ 458 BATU_VP) 459 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ 460 BATL_PP_RW |\ 461 BATL_MEMCOHERENCE) 462 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 463 464 /* 465 * BAT7 64M Cache-inhibited, guarded 466 * 0xe800_0000 64K NAND FLASH 467 * 0xe804_0000 128K DUART Registers 468 */ 469 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ 470 BATL_PP_RW |\ 471 BATL_CACHEINHIBIT |\ 472 BATL_GUARDEDSTORAGE) 473 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ 474 BATU_BL_512K |\ 475 BATU_VS |\ 476 BATU_VP) 477 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ 478 BATL_PP_RW |\ 479 BATL_CACHEINHIBIT) 480 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 481 482 /* 483 * Miscellaneous configurable options 484 */ 485 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 486 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 487 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ 488 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 489 #define CONFIG_PREBOOT /* enable preboot variable */ 490 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 491 492 /* 493 * For booting Linux, the board info and command line data 494 * have to be in the first 16 MB of memory, since this is 495 * the maximum mapped by the Linux kernel during initialization. 496 */ 497 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 498 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 499 500 /* 501 * Environment Configuration 502 */ 503 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 504 #define CONFIG_ENV_SIZE 0x8000 505 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 506 507 /* 508 * Flash memory map: 509 * fffc0000 - ffffffff Pri FDT (256KB) 510 * fff80000 - fffbffff Pri U-Boot Environment (256 KB) 511 * fff00000 - fff7ffff Pri U-Boot (512 KB) 512 * fef00000 - ffefffff Pri OS image (16MB) 513 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 514 * 515 * f7fc0000 - f7ffffff Sec FDT (256KB) 516 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) 517 * f7f00000 - f7f7ffff Sec U-Boot (512 KB) 518 * f6f00000 - f7efffff Sec OS image (16MB) 519 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 520 */ 521 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000) 522 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000) 523 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000) 524 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000) 525 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 526 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 527 528 #define CONFIG_PROG_UBOOT1 \ 529 "$download_cmd $loadaddr $ubootfile; " \ 530 "if test $? -eq 0; then " \ 531 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 532 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 533 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 534 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 535 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 536 "if test $? -ne 0; then " \ 537 "echo PROGRAM FAILED; " \ 538 "else; " \ 539 "echo PROGRAM SUCCEEDED; " \ 540 "fi; " \ 541 "else; " \ 542 "echo DOWNLOAD FAILED; " \ 543 "fi;" 544 545 #define CONFIG_PROG_UBOOT2 \ 546 "$download_cmd $loadaddr $ubootfile; " \ 547 "if test $? -eq 0; then " \ 548 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 549 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 550 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 551 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 552 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 553 "if test $? -ne 0; then " \ 554 "echo PROGRAM FAILED; " \ 555 "else; " \ 556 "echo PROGRAM SUCCEEDED; " \ 557 "fi; " \ 558 "else; " \ 559 "echo DOWNLOAD FAILED; " \ 560 "fi;" 561 562 #define CONFIG_BOOT_OS_NET \ 563 "$download_cmd $osaddr $osfile; " \ 564 "if test $? -eq 0; then " \ 565 "if test -n $fdtaddr; then " \ 566 "$download_cmd $fdtaddr $fdtfile; " \ 567 "if test $? -eq 0; then " \ 568 "bootm $osaddr - $fdtaddr; " \ 569 "else; " \ 570 "echo FDT DOWNLOAD FAILED; " \ 571 "fi; " \ 572 "else; " \ 573 "bootm $osaddr; " \ 574 "fi; " \ 575 "else; " \ 576 "echo OS DOWNLOAD FAILED; " \ 577 "fi;" 578 579 #define CONFIG_PROG_OS1 \ 580 "$download_cmd $osaddr $osfile; " \ 581 "if test $? -eq 0; then " \ 582 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 583 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 584 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 585 "if test $? -ne 0; then " \ 586 "echo OS PROGRAM FAILED; " \ 587 "else; " \ 588 "echo OS PROGRAM SUCCEEDED; " \ 589 "fi; " \ 590 "else; " \ 591 "echo OS DOWNLOAD FAILED; " \ 592 "fi;" 593 594 #define CONFIG_PROG_OS2 \ 595 "$download_cmd $osaddr $osfile; " \ 596 "if test $? -eq 0; then " \ 597 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 598 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 599 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 600 "if test $? -ne 0; then " \ 601 "echo OS PROGRAM FAILED; " \ 602 "else; " \ 603 "echo OS PROGRAM SUCCEEDED; " \ 604 "fi; " \ 605 "else; " \ 606 "echo OS DOWNLOAD FAILED; " \ 607 "fi;" 608 609 #define CONFIG_PROG_FDT1 \ 610 "$download_cmd $fdtaddr $fdtfile; " \ 611 "if test $? -eq 0; then " \ 612 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 613 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 614 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 615 "if test $? -ne 0; then " \ 616 "echo FDT PROGRAM FAILED; " \ 617 "else; " \ 618 "echo FDT PROGRAM SUCCEEDED; " \ 619 "fi; " \ 620 "else; " \ 621 "echo FDT DOWNLOAD FAILED; " \ 622 "fi;" 623 624 #define CONFIG_PROG_FDT2 \ 625 "$download_cmd $fdtaddr $fdtfile; " \ 626 "if test $? -eq 0; then " \ 627 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 628 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 629 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 630 "if test $? -ne 0; then " \ 631 "echo FDT PROGRAM FAILED; " \ 632 "else; " \ 633 "echo FDT PROGRAM SUCCEEDED; " \ 634 "fi; " \ 635 "else; " \ 636 "echo FDT DOWNLOAD FAILED; " \ 637 "fi;" 638 639 #define CONFIG_EXTRA_ENV_SETTINGS \ 640 "autoload=yes\0" \ 641 "download_cmd=tftp\0" \ 642 "console_args=console=ttyS0,115200\0" \ 643 "root_args=root=/dev/nfs rw\0" \ 644 "misc_args=ip=on\0" \ 645 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 646 "bootfile=/home/user/file\0" \ 647 "osfile=/home/user/board.uImage\0" \ 648 "fdtfile=/home/user/board.dtb\0" \ 649 "ubootfile=/home/user/u-boot.bin\0" \ 650 "fdtaddr=0x1e00000\0" \ 651 "osaddr=0x1000000\0" \ 652 "loadaddr=0x1000000\0" \ 653 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 654 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 655 "prog_os1="CONFIG_PROG_OS1"\0" \ 656 "prog_os2="CONFIG_PROG_OS2"\0" \ 657 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 658 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 659 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 660 "bootcmd_flash1=run set_bootargs; " \ 661 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 662 "bootcmd_flash2=run set_bootargs; " \ 663 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 664 "bootcmd=run bootcmd_flash1\0" 665 #endif /* __CONFIG_H */ 666