1 /* 2 * Copyright 2009 Extreme Engineering Solutions, Inc. 3 * Copyright 2007-2008 Freescale Semiconductor, Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * xpedite517x board configuration file 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_MPC8641 1 /* MPC8641 specific */ 18 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */ 19 #define CONFIG_SYS_BOARD_NAME "XPedite5170" 20 #define CONFIG_SYS_FORM_3U_VPX 1 21 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 22 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ 23 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 24 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ 25 #define CONFIG_ALTIVEC 1 26 #define CONFIG_SYS_GENERIC_BOARD 27 #define CONFIG_DISPLAY_BOARDINFO 28 29 #define CONFIG_SYS_TEXT_BASE 0xfff00000 30 31 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 32 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ 33 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ 34 #define CONFIG_PCIE1 1 /* PCIE controler 1 */ 35 #define CONFIG_PCIE2 1 /* PCIE controler 2 */ 36 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 37 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 38 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 39 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 40 41 /* 42 * DDR config 43 */ 44 #define CONFIG_SYS_FSL_DDR2 45 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 46 #define CONFIG_DDR_SPD 47 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 48 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ 49 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ 50 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ 51 #define CONFIG_NUM_DDR_CONTROLLERS 2 52 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 53 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 54 #define CONFIG_DDR_ECC 55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 56 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 57 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 58 #define CONFIG_VERY_BIG_RAM 59 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 60 61 /* 62 * virtual address to be used for temporary mappings. There 63 * should be 128k free at this VA. 64 */ 65 #define CONFIG_SYS_SCRATCH_VA 0xe0000000 66 67 #ifndef __ASSEMBLY__ 68 extern unsigned long get_board_sys_clk(unsigned long dummy); 69 #endif 70 71 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ 72 73 /* 74 * L2CR setup 75 */ 76 #define CONFIG_SYS_L2 77 #define L2_INIT 0 78 #define L2_ENABLE (L2CR_L2E) 79 80 /* 81 * Base addresses -- Note these are effective addresses where the 82 * actual resources get mapped (not physical addresses) 83 */ 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 85 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ 86 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 87 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 88 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 89 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 90 91 /* 92 * Diagnostics 93 */ 94 #define CONFIG_SYS_ALT_MEMTEST 95 #define CONFIG_SYS_MEMTEST_START 0x10000000 96 #define CONFIG_SYS_MEMTEST_END 0x20000000 97 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\ 98 CONFIG_SYS_POST_I2C) 99 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \ 100 CONFIG_SYS_I2C_DS4510_ADDR, \ 101 CONFIG_SYS_I2C_EEPROM_ADDR, \ 102 CONFIG_SYS_I2C_LM90_ADDR, \ 103 CONFIG_SYS_I2C_PCA9553_ADDR, \ 104 CONFIG_SYS_I2C_PCA953X_ADDR0, \ 105 CONFIG_SYS_I2C_PCA953X_ADDR1, \ 106 CONFIG_SYS_I2C_PCA953X_ADDR2, \ 107 CONFIG_SYS_I2C_PCA953X_ADDR3, \ 108 CONFIG_SYS_I2C_PEX8518_ADDR, \ 109 CONFIG_SYS_I2C_RTC_ADDR} 110 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */ 111 #define I2C_ADDR_IGNORE_LIST {0x50} 112 113 /* 114 * Memory map 115 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 116 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable 117 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable 118 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable 119 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable 120 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable 121 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable 122 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable 123 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable 124 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable 125 */ 126 127 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) 128 129 /* 130 * NAND flash configuration 131 */ 132 #define CONFIG_SYS_NAND_BASE 0xef800000 133 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ 134 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} 135 #define CONFIG_SYS_MAX_NAND_DEVICE 2 136 #define CONFIG_NAND_ACTL 137 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ 138 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ 139 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ 140 #define CONFIG_SYS_NAND_ACTL_DELAY 25 141 #define CONFIG_JFFS2_NAND 142 143 /* 144 * NOR flash configuration 145 */ 146 #define CONFIG_SYS_FLASH_BASE 0xf8000000 147 #define CONFIG_SYS_FLASH_BASE2 0xf0000000 148 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 149 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 150 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 151 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 152 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 153 #define CONFIG_FLASH_CFI_DRIVER 154 #define CONFIG_SYS_FLASH_CFI 155 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 156 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ 157 {0xf7f00000, 0xc0000} } 158 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 159 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 160 161 /* 162 * Chip select configuration 163 */ 164 /* NOR Flash 0 on CS0 */ 165 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ 166 BR_PS_16 |\ 167 BR_V) 168 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ 169 OR_GPCM_CSNT |\ 170 OR_GPCM_XACS |\ 171 OR_GPCM_ACS_DIV2 |\ 172 OR_GPCM_SCY_8 |\ 173 OR_GPCM_TRLX |\ 174 OR_GPCM_EHTR |\ 175 OR_GPCM_EAD) 176 177 /* NOR Flash 1 on CS1 */ 178 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ 179 BR_PS_16 |\ 180 BR_V) 181 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 182 183 /* NAND flash on CS2 */ 184 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ 185 BR_PS_8 |\ 186 BR_V) 187 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ 188 OR_GPCM_BCTLD |\ 189 OR_GPCM_CSNT |\ 190 OR_GPCM_ACS_DIV4 |\ 191 OR_GPCM_SCY_4 |\ 192 OR_GPCM_TRLX |\ 193 OR_GPCM_EHTR) 194 195 /* Optional NAND flash on CS3 */ 196 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ 197 BR_PS_8 |\ 198 BR_V) 199 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 200 201 /* 202 * Use L1 as initial stack 203 */ 204 #define CONFIG_SYS_INIT_RAM_LOCK 1 205 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 206 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 207 208 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 210 211 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 212 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 213 214 /* 215 * Serial Port 216 */ 217 #define CONFIG_CONS_INDEX 1 218 #define CONFIG_SYS_NS16550 219 #define CONFIG_SYS_NS16550_SERIAL 220 #define CONFIG_SYS_NS16550_REG_SIZE 1 221 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 224 #define CONFIG_SYS_BAUDRATE_TABLE \ 225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 226 #define CONFIG_BAUDRATE 115200 227 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 228 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 229 230 /* 231 * Use the HUSH parser 232 */ 233 #define CONFIG_SYS_HUSH_PARSER 234 235 /* 236 * Pass open firmware flat tree 237 */ 238 #define CONFIG_OF_LIBFDT 1 239 #define CONFIG_OF_BOARD_SETUP 1 240 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 241 242 /* 243 * I2C 244 */ 245 #define CONFIG_SYS_I2C 246 #define CONFIG_SYS_I2C_FSL 247 #define CONFIG_SYS_FSL_I2C_SPEED 100000 248 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 249 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 250 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 251 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 252 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 253 254 /* PEX8518 slave I2C interface */ 255 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 256 257 /* I2C DS1631 temperature sensor */ 258 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 259 #define CONFIG_DTT_DS1621 260 #define CONFIG_DTT_SENSORS { 0 } 261 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c 262 263 /* I2C EEPROM - AT24C128B */ 264 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 265 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 267 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ 268 269 /* I2C RTC */ 270 #define CONFIG_RTC_M41T11 1 271 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 272 #define CONFIG_SYS_M41T11_BASE_YEAR 2000 273 274 /* GPIO/EEPROM/SRAM */ 275 #define CONFIG_DS4510 276 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 277 278 /* GPIO */ 279 #define CONFIG_PCA953X 280 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 281 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c 282 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e 283 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f 284 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 285 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62 286 287 /* 288 * PU = pulled high, PD = pulled low 289 * I = input, O = output, IO = input/output 290 */ 291 /* PCA9557 @ 0x18*/ 292 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ 293 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ 294 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ 295 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ 296 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ 297 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ 298 299 /* PCA9557 @ 0x1c*/ 300 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ 301 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ 302 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ 303 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ 304 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ 305 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ 306 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ 307 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ 308 309 /* PCA9557 @ 0x1e*/ 310 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ 311 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ 312 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ 313 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ 314 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ 315 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ 316 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ 317 318 /* PCA9557 @ 0x1f */ 319 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ 320 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ 321 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ 322 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ 323 324 /* 325 * General PCI 326 * Memory space is mapped 1-1, but I/O space must start from 0. 327 */ 328 /* PCIE1 - PEX8518 */ 329 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 330 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 331 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ 332 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 333 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 334 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 335 336 /* PCIE2 - VPX P1 */ 337 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 338 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 339 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 340 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 341 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 342 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ 343 344 /* 345 * Networking options 346 */ 347 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 348 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 349 #define CONFIG_MII 1 /* MII PHY management */ 350 #define CONFIG_ETHPRIME "eTSEC1" 351 352 #define CONFIG_TSEC1 1 353 #define CONFIG_TSEC1_NAME "eTSEC1" 354 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 355 #define TSEC1_PHY_ADDR 1 356 #define TSEC1_PHYIDX 0 357 #define CONFIG_HAS_ETH0 358 359 #define CONFIG_TSEC2 1 360 #define CONFIG_TSEC2_NAME "eTSEC2" 361 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 362 #define TSEC2_PHY_ADDR 2 363 #define TSEC2_PHYIDX 0 364 #define CONFIG_HAS_ETH1 365 366 /* 367 * BAT mappings 368 */ 369 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 370 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ 371 BATL_PP_RW |\ 372 BATL_CACHEINHIBIT |\ 373 BATL_GUARDEDSTORAGE) 374 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ 375 BATU_BL_1M |\ 376 BATU_VS |\ 377 BATU_VP) 378 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ 379 BATL_PP_RW |\ 380 BATL_CACHEINHIBIT) 381 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 382 #endif 383 384 /* 385 * BAT0 2G Cacheable, non-guarded 386 * 0x0000_0000 2G DDR 387 */ 388 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 389 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) 390 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) 391 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 392 393 /* 394 * BAT1 1G Cache-inhibited, guarded 395 * 0x8000_0000 1G PCI-Express 1 Memory 396 */ 397 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ 398 BATL_PP_RW |\ 399 BATL_CACHEINHIBIT |\ 400 BATL_GUARDEDSTORAGE) 401 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ 402 BATU_BL_1G |\ 403 BATU_VS |\ 404 BATU_VP) 405 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ 406 BATL_PP_RW |\ 407 BATL_CACHEINHIBIT) 408 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 409 410 /* 411 * BAT2 512M Cache-inhibited, guarded 412 * 0xc000_0000 512M PCI-Express 2 Memory 413 */ 414 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ 415 BATL_PP_RW |\ 416 BATL_CACHEINHIBIT |\ 417 BATL_GUARDEDSTORAGE) 418 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ 419 BATU_BL_512M |\ 420 BATU_VS |\ 421 BATU_VP) 422 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ 423 BATL_PP_RW |\ 424 BATL_CACHEINHIBIT) 425 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 426 427 /* 428 * BAT3 1M Cache-inhibited, guarded 429 * 0xe000_0000 1M CCSR 430 */ 431 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ 432 BATL_PP_RW |\ 433 BATL_CACHEINHIBIT |\ 434 BATL_GUARDEDSTORAGE) 435 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ 436 BATU_BL_1M |\ 437 BATU_VS |\ 438 BATU_VP) 439 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ 440 BATL_PP_RW |\ 441 BATL_CACHEINHIBIT) 442 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 443 444 /* 445 * BAT4 32M Cache-inhibited, guarded 446 * 0xe200_0000 16M PCI-Express 1 I/O 447 * 0xe300_0000 16M PCI-Express 2 I/0 448 */ 449 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ 450 BATL_PP_RW |\ 451 BATL_CACHEINHIBIT |\ 452 BATL_GUARDEDSTORAGE) 453 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ 454 BATU_BL_32M |\ 455 BATU_VS |\ 456 BATU_VP) 457 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ 458 BATL_PP_RW |\ 459 BATL_CACHEINHIBIT) 460 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 461 462 /* 463 * BAT5 128K Cacheable, non-guarded 464 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) 465 */ 466 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ 467 BATL_PP_RW |\ 468 BATL_MEMCOHERENCE) 469 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ 470 BATU_BL_128K |\ 471 BATU_VS |\ 472 BATU_VP) 473 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 474 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 475 476 /* 477 * BAT6 256M Cache-inhibited, guarded 478 * 0xf000_0000 256M FLASH 479 */ 480 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ 481 BATL_PP_RW |\ 482 BATL_CACHEINHIBIT |\ 483 BATL_GUARDEDSTORAGE) 484 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ 485 BATU_BL_256M |\ 486 BATU_VS |\ 487 BATU_VP) 488 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ 489 BATL_PP_RW |\ 490 BATL_MEMCOHERENCE) 491 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 492 493 /* Map the last 1M of flash where we're running from reset */ 494 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ 495 BATL_PP_RW |\ 496 BATL_CACHEINHIBIT |\ 497 BATL_GUARDEDSTORAGE) 498 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\ 499 BATU_BL_1M |\ 500 BATU_VS |\ 501 BATU_VP) 502 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ 503 BATL_PP_RW |\ 504 BATL_MEMCOHERENCE) 505 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 506 507 /* 508 * BAT7 64M Cache-inhibited, guarded 509 * 0xe800_0000 64K NAND FLASH 510 * 0xe804_0000 128K DUART Registers 511 */ 512 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ 513 BATL_PP_RW |\ 514 BATL_CACHEINHIBIT |\ 515 BATL_GUARDEDSTORAGE) 516 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ 517 BATU_BL_512K |\ 518 BATU_VS |\ 519 BATU_VP) 520 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ 521 BATL_PP_RW |\ 522 BATL_CACHEINHIBIT) 523 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 524 525 /* 526 * Command configuration. 527 */ 528 #define CONFIG_CMD_ASKENV 529 #define CONFIG_CMD_DATE 530 #define CONFIG_CMD_DHCP 531 #define CONFIG_CMD_DS4510 532 #define CONFIG_CMD_DS4510_INFO 533 #define CONFIG_CMD_DTT 534 #define CONFIG_CMD_EEPROM 535 #define CONFIG_CMD_ELF 536 #define CONFIG_CMD_I2C 537 #define CONFIG_CMD_IRQ 538 #define CONFIG_CMD_JFFS2 539 #define CONFIG_CMD_MII 540 #define CONFIG_CMD_NAND 541 #define CONFIG_CMD_PCA953X 542 #define CONFIG_CMD_PCA953X_INFO 543 #define CONFIG_CMD_PCI 544 #define CONFIG_CMD_PCI_ENUM 545 #define CONFIG_CMD_PING 546 #define CONFIG_CMD_REGINFO 547 #define CONFIG_CMD_SNTP 548 549 /* 550 * Miscellaneous configurable options 551 */ 552 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 553 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 554 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 555 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 556 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 557 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 558 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */ 559 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ 560 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ 561 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 562 #define CONFIG_PREBOOT /* enable preboot variable */ 563 #define CONFIG_FIT 1 564 #define CONFIG_FIT_VERBOSE 1 565 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ 566 567 /* 568 * For booting Linux, the board info and command line data 569 * have to be in the first 16 MB of memory, since this is 570 * the maximum mapped by the Linux kernel during initialization. 571 */ 572 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 573 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 574 575 /* 576 * Environment Configuration 577 */ 578 #define CONFIG_ENV_IS_IN_FLASH 1 579 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ 580 #define CONFIG_ENV_SIZE 0x8000 581 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 582 583 /* 584 * Flash memory map: 585 * fffc0000 - ffffffff Pri FDT (256KB) 586 * fff80000 - fffbffff Pri U-Boot Environment (256 KB) 587 * fff00000 - fff7ffff Pri U-Boot (512 KB) 588 * fef00000 - ffefffff Pri OS image (16MB) 589 * f8000000 - feefffff Pri OS Use/Filesystem (111MB) 590 * 591 * f7fc0000 - f7ffffff Sec FDT (256KB) 592 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) 593 * f7f00000 - f7f7ffff Sec U-Boot (512 KB) 594 * f6f00000 - f7efffff Sec OS image (16MB) 595 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) 596 */ 597 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000) 598 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000) 599 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000) 600 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000) 601 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) 602 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) 603 604 #define CONFIG_PROG_UBOOT1 \ 605 "$download_cmd $loadaddr $ubootfile; " \ 606 "if test $? -eq 0; then " \ 607 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 608 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 609 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ 610 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ 611 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ 612 "if test $? -ne 0; then " \ 613 "echo PROGRAM FAILED; " \ 614 "else; " \ 615 "echo PROGRAM SUCCEEDED; " \ 616 "fi; " \ 617 "else; " \ 618 "echo DOWNLOAD FAILED; " \ 619 "fi;" 620 621 #define CONFIG_PROG_UBOOT2 \ 622 "$download_cmd $loadaddr $ubootfile; " \ 623 "if test $? -eq 0; then " \ 624 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 625 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 626 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ 627 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ 628 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ 629 "if test $? -ne 0; then " \ 630 "echo PROGRAM FAILED; " \ 631 "else; " \ 632 "echo PROGRAM SUCCEEDED; " \ 633 "fi; " \ 634 "else; " \ 635 "echo DOWNLOAD FAILED; " \ 636 "fi;" 637 638 #define CONFIG_BOOT_OS_NET \ 639 "$download_cmd $osaddr $osfile; " \ 640 "if test $? -eq 0; then " \ 641 "if test -n $fdtaddr; then " \ 642 "$download_cmd $fdtaddr $fdtfile; " \ 643 "if test $? -eq 0; then " \ 644 "bootm $osaddr - $fdtaddr; " \ 645 "else; " \ 646 "echo FDT DOWNLOAD FAILED; " \ 647 "fi; " \ 648 "else; " \ 649 "bootm $osaddr; " \ 650 "fi; " \ 651 "else; " \ 652 "echo OS DOWNLOAD FAILED; " \ 653 "fi;" 654 655 #define CONFIG_PROG_OS1 \ 656 "$download_cmd $osaddr $osfile; " \ 657 "if test $? -eq 0; then " \ 658 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ 659 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 660 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ 661 "if test $? -ne 0; then " \ 662 "echo OS PROGRAM FAILED; " \ 663 "else; " \ 664 "echo OS PROGRAM SUCCEEDED; " \ 665 "fi; " \ 666 "else; " \ 667 "echo OS DOWNLOAD FAILED; " \ 668 "fi;" 669 670 #define CONFIG_PROG_OS2 \ 671 "$download_cmd $osaddr $osfile; " \ 672 "if test $? -eq 0; then " \ 673 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ 674 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 675 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ 676 "if test $? -ne 0; then " \ 677 "echo OS PROGRAM FAILED; " \ 678 "else; " \ 679 "echo OS PROGRAM SUCCEEDED; " \ 680 "fi; " \ 681 "else; " \ 682 "echo OS DOWNLOAD FAILED; " \ 683 "fi;" 684 685 #define CONFIG_PROG_FDT1 \ 686 "$download_cmd $fdtaddr $fdtfile; " \ 687 "if test $? -eq 0; then " \ 688 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ 689 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 690 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ 691 "if test $? -ne 0; then " \ 692 "echo FDT PROGRAM FAILED; " \ 693 "else; " \ 694 "echo FDT PROGRAM SUCCEEDED; " \ 695 "fi; " \ 696 "else; " \ 697 "echo FDT DOWNLOAD FAILED; " \ 698 "fi;" 699 700 #define CONFIG_PROG_FDT2 \ 701 "$download_cmd $fdtaddr $fdtfile; " \ 702 "if test $? -eq 0; then " \ 703 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ 704 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 705 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ 706 "if test $? -ne 0; then " \ 707 "echo FDT PROGRAM FAILED; " \ 708 "else; " \ 709 "echo FDT PROGRAM SUCCEEDED; " \ 710 "fi; " \ 711 "else; " \ 712 "echo FDT DOWNLOAD FAILED; " \ 713 "fi;" 714 715 #define CONFIG_EXTRA_ENV_SETTINGS \ 716 "autoload=yes\0" \ 717 "download_cmd=tftp\0" \ 718 "console_args=console=ttyS0,115200\0" \ 719 "root_args=root=/dev/nfs rw\0" \ 720 "misc_args=ip=on\0" \ 721 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ 722 "bootfile=/home/user/file\0" \ 723 "osfile=/home/user/board.uImage\0" \ 724 "fdtfile=/home/user/board.dtb\0" \ 725 "ubootfile=/home/user/u-boot.bin\0" \ 726 "fdtaddr=c00000\0" \ 727 "osaddr=0x1000000\0" \ 728 "loadaddr=0x1000000\0" \ 729 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ 730 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ 731 "prog_os1="CONFIG_PROG_OS1"\0" \ 732 "prog_os2="CONFIG_PROG_OS2"\0" \ 733 "prog_fdt1="CONFIG_PROG_FDT1"\0" \ 734 "prog_fdt2="CONFIG_PROG_FDT2"\0" \ 735 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ 736 "bootcmd_flash1=run set_bootargs; " \ 737 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ 738 "bootcmd_flash2=run set_bootargs; " \ 739 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ 740 "bootcmd=run bootcmd_flash1\0" 741 #endif /* __CONFIG_H */ 742