1*2678059eSSiva Durga Prasad Paladugu /* 2*2678059eSSiva Durga Prasad Paladugu * Configuration for Xilinx ZynqMP eMMC Flash utility 3*2678059eSSiva Durga Prasad Paladugu * 4*2678059eSSiva Durga Prasad Paladugu * (C) Copyright 2018 Xilinx, Inc. 5*2678059eSSiva Durga Prasad Paladugu * Michal Simek <michal.simek@xilinx.com> 6*2678059eSSiva Durga Prasad Paladugu * Siva Durga Prasad Paladugu <sivadur@xilinx.com> 7*2678059eSSiva Durga Prasad Paladugu * 8*2678059eSSiva Durga Prasad Paladugu * SPDX-License-Identifier: GPL-2.0+ 9*2678059eSSiva Durga Prasad Paladugu */ 10*2678059eSSiva Durga Prasad Paladugu 11*2678059eSSiva Durga Prasad Paladugu #ifndef __CONFIG_ZYNQMP_MINI_EMMC_H 12*2678059eSSiva Durga Prasad Paladugu #define __CONFIG_ZYNQMP_MINI_EMMC_H 13*2678059eSSiva Durga Prasad Paladugu 14*2678059eSSiva Durga Prasad Paladugu #include <configs/xilinx_zynqmp_mini.h> 15*2678059eSSiva Durga Prasad Paladugu 16*2678059eSSiva Durga Prasad Paladugu #define CONFIG_SYS_ICACHE_OFF 17*2678059eSSiva Durga Prasad Paladugu #define CONFIG_NR_DRAM_BANKS 1 18*2678059eSSiva Durga Prasad Paladugu #define CONFIG_ENV_SIZE 0x10000 19*2678059eSSiva Durga Prasad Paladugu #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 20*2678059eSSiva Durga Prasad Paladugu #define CONFIG_SYS_MALLOC_LEN 0x800000 21*2678059eSSiva Durga Prasad Paladugu #define CONFIG_SYS_LONGHELP 22*2678059eSSiva Durga Prasad Paladugu 23*2678059eSSiva Durga Prasad Paladugu #endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ 24