1 /*
2  *
3  * Copyright (c) 2015 Google, Inc
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _X86_CHROMEBOOK_H
9 #define _X86_CHROMEBOOK_H
10 
11 #define CONFIG_SYS_MONITOR_LEN			(1 << 20)
12 
13 #define CONFIG_BOARD_EARLY_INIT_F
14 #define CONFIG_MISC_INIT_R
15 
16 #define CONFIG_X86_MRC_ADDR			0xfffa0000
17 #define CONFIG_CACHE_MRC_SIZE_KB		512
18 
19 #define CONFIG_SCSI_DEV_LIST	\
20 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
21 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
22 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
23 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
24 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
25 
26 #define CONFIG_PCI_MEM_BUS	0xe0000000
27 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
28 #define CONFIG_PCI_MEM_SIZE	0x10000000
29 
30 #define CONFIG_PCI_PREF_BUS	0xd0000000
31 #define CONFIG_PCI_PREF_PHYS	CONFIG_PCI_PREF_BUS
32 #define CONFIG_PCI_PREF_SIZE	0x10000000
33 
34 #define CONFIG_PCI_IO_BUS	0x1000
35 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
36 #define CONFIG_PCI_IO_SIZE	0xefff
37 
38 #define CONFIG_PCI_PNP
39 
40 #define CONFIG_BIOSEMU
41 #define VIDEO_IO_OFFSET				0
42 #define CONFIG_X86EMU_RAW_IO
43 
44 #define CONFIG_ARCH_EARLY_INIT_R
45 
46 #undef CONFIG_ENV_IS_NOWHERE
47 #undef CONFIG_ENV_SIZE
48 #define CONFIG_ENV_SIZE			0x1000
49 #define CONFIG_ENV_SECT_SIZE		0x1000
50 #define CONFIG_ENV_IS_IN_SPI_FLASH
51 #define CONFIG_ENV_OFFSET		0x003f8000
52 
53 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,i8042-kbd,serial\0" \
54 					"stdout=vga,serial\0" \
55 					"stderr=vga,serial\0"
56 
57 #endif
58