1 /* 2 * 3 * Copyright (c) 2015 Google, Inc 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _X86_CHROMEBOOK_H 9 #define _X86_CHROMEBOOK_H 10 11 #define CONFIG_SYS_MONITOR_LEN (1 << 20) 12 13 #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 14 #define CONFIG_BOARD_EARLY_INIT_F 15 #define CONFIG_MISC_INIT_R 16 17 #define CONFIG_X86_MRC_ADDR 0xfffa0000 18 #define CONFIG_CACHE_MRC_SIZE_KB 512 19 20 #define CONFIG_X86_SERIAL 21 22 #define CONFIG_SCSI_DEV_LIST \ 23 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ 24 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ 25 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ 26 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \ 27 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI} 28 29 #define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin 30 #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 31 32 #define CONFIG_PCI_MEM_BUS 0xe0000000 33 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 34 #define CONFIG_PCI_MEM_SIZE 0x10000000 35 36 #define CONFIG_PCI_PREF_BUS 0xd0000000 37 #define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS 38 #define CONFIG_PCI_PREF_SIZE 0x10000000 39 40 #define CONFIG_PCI_IO_BUS 0x1000 41 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 42 #define CONFIG_PCI_IO_SIZE 0xefff 43 44 #define CONFIG_SYS_EARLY_PCI_INIT 45 #define CONFIG_PCI_PNP 46 47 #define CONFIG_BIOSEMU 48 #define VIDEO_IO_OFFSET 0 49 #define CONFIG_X86EMU_RAW_IO 50 51 #define CONFIG_CROS_EC 52 #define CONFIG_CROS_EC_LPC 53 #define CONFIG_CMD_CROS_EC 54 #define CONFIG_ARCH_EARLY_INIT_R 55 56 #undef CONFIG_ENV_IS_NOWHERE 57 #undef CONFIG_ENV_SIZE 58 #define CONFIG_ENV_SIZE 0x1000 59 #define CONFIG_ENV_SECT_SIZE 0x1000 60 #define CONFIG_ENV_IS_IN_SPI_FLASH 61 #define CONFIG_ENV_OFFSET 0x003f8000 62 63 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ 64 "stdout=vga,serial\0" \ 65 "stderr=vga,serial\0" 66 67 #endif 68