1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4 * 5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 18 #define CONFIG_X600 /* on X600 board */ 19 #define CONFIG_SYS_GENERIC_BOARD 20 #define CONFIG_SYS_THUMB_BUILD 21 22 #include <asm/arch/hardware.h> 23 24 /* Timer, HZ specific defines */ 25 #define CONFIG_SYS_HZ_CLOCK 8300000 26 27 #define CONFIG_SYS_TEXT_BASE 0x00800040 28 #define CONFIG_SYS_FLASH_BASE 0xf8000000 29 /* Reserve 8KiB for SPL */ 30 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 31 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 32 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 33 CONFIG_SYS_SPL_LEN) 34 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 35 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 36 #define CONFIG_SYS_MONITOR_LEN 0x60000 37 38 #define CONFIG_ENV_IS_IN_FLASH 39 40 /* Serial Configuration (PL011) */ 41 #define CONFIG_SYS_SERIAL0 0xD0000000 42 #define CONFIG_SYS_SERIAL1 0xD0080000 43 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 44 (void *)CONFIG_SYS_SERIAL1 } 45 #define CONFIG_PL011_SERIAL 46 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 47 #define CONFIG_CONS_INDEX 0 48 #define CONFIG_BAUDRATE 115200 49 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 50 57600, 115200 } 51 #define CONFIG_SYS_LOADS_BAUD_CHANGE 52 53 /* NOR FLASH config options */ 54 #define CONFIG_ST_SMI 55 #define CONFIG_SYS_MAX_FLASH_BANKS 1 56 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 57 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 58 #define CONFIG_SYS_MAX_FLASH_SECT 128 59 #define CONFIG_SYS_FLASH_EMPTY_INFO 60 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 61 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 62 63 /* NAND FLASH config options */ 64 #define CONFIG_NAND_FSMC 65 #define CONFIG_SYS_NAND_SELF_INIT 66 #define CONFIG_SYS_MAX_NAND_DEVICE 1 67 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 68 #define CONFIG_MTD_ECC_SOFT 69 #define CONFIG_SYS_FSMC_NAND_8BIT 70 #define CONFIG_SYS_NAND_ONFI_DETECTION 71 #define CONFIG_NAND_ECC_BCH 72 #define CONFIG_BCH 73 74 /* UBI/UBI config options */ 75 #define CONFIG_MTD_DEVICE 76 #define CONFIG_MTD_PARTITIONS 77 #define CONFIG_RBTREE 78 79 /* Ethernet config options */ 80 #define CONFIG_MII 81 #define CONFIG_PHYLIB 82 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 83 #define CONFIG_PHY_ADDR 0 /* PHY address */ 84 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 85 86 #define CONFIG_SPEAR_GPIO 87 88 /* I2C config options */ 89 #define CONFIG_SYS_I2C 90 #define CONFIG_SYS_I2C_DW 91 #define CONFIG_SYS_I2C_BASE 0xD0200000 92 #define CONFIG_SYS_I2C_SPEED 400000 93 #define CONFIG_SYS_I2C_SLAVE 0x02 94 #define CONFIG_I2C_CHIPADDRESS 0x50 95 96 #define CONFIG_RTC_M41T62 1 97 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 98 99 /* FPGA config options */ 100 #define CONFIG_FPGA 101 #define CONFIG_FPGA_XILINX 102 #define CONFIG_FPGA_SPARTAN3 103 #define CONFIG_FPGA_COUNT 1 104 105 /* USB EHCI options */ 106 #define CONFIG_USB_EHCI 107 #define CONFIG_USB_EHCI_SPEAR 108 #define CONFIG_USB_STORAGE 109 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 110 111 /* 112 * Command support defines 113 */ 114 #define CONFIG_CMD_CACHE 115 #define CONFIG_CMD_DATE 116 #define CONFIG_CMD_DHCP 117 #define CONFIG_CMD_ENV 118 #define CONFIG_CMD_FAT 119 #define CONFIG_CMD_FPGA_LOADMK 120 #define CONFIG_CMD_FS_GENERIC 121 #define CONFIG_CMD_GPIO 122 #define CONFIG_CMD_I2C 123 #define CONFIG_CMD_MII 124 #define CONFIG_CMD_MTDPARTS 125 #define CONFIG_CMD_NAND 126 #define CONFIG_CMD_PING 127 #define CONFIG_CMD_SAVES 128 #define CONFIG_CMD_UBI 129 #define CONFIG_CMD_UBIFS 130 #define CONFIG_CMD_USB 131 #define CONFIG_LZO 132 133 /* Filesystem support (for USB key) */ 134 #define CONFIG_SUPPORT_VFAT 135 #define CONFIG_DOS_PARTITION 136 137 #define CONFIG_BOOTDELAY 3 138 139 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 140 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 141 142 /* 143 * U-Boot Environment placing definitions. 144 */ 145 #define CONFIG_ENV_SECT_SIZE 0x00010000 146 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 147 CONFIG_SYS_MONITOR_LEN) 148 #define CONFIG_ENV_SIZE 0x02000 149 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 150 CONFIG_ENV_SECT_SIZE) 151 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 152 153 /* Miscellaneous configurable options */ 154 #define CONFIG_ARCH_CPU_INIT 155 #define CONFIG_DISPLAY_CPUINFO 156 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 157 #define CONFIG_CMDLINE_TAG 158 #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 159 #define CONFIG_SETUP_MEMORY_TAGS 160 #define CONFIG_MISC_INIT_R 161 #define CONFIG_BOARD_LATE_INIT 162 #define CONFIG_LOOPW /* enable loopw command */ 163 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 164 #define CONFIG_ZERO_BOOTDELAY_CHECK 165 166 #define CONFIG_SYS_MEMTEST_START 0x00800000 167 #define CONFIG_SYS_MEMTEST_END 0x04000000 168 #define CONFIG_SYS_MALLOC_LEN (8 << 20) 169 #define CONFIG_IDENT_STRING "-SPEAr" 170 #define CONFIG_SYS_LONGHELP 171 #define CONFIG_CMDLINE_EDITING 172 #define CONFIG_AUTO_COMPLETE 173 #define CONFIG_SYS_CBSIZE 256 174 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 175 sizeof(CONFIG_SYS_PROMPT) + 16) 176 #define CONFIG_SYS_MAXARGS 16 177 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 178 #define CONFIG_SYS_LOAD_ADDR 0x00800000 179 #define CONFIG_SYS_CONSOLE_INFO_QUIET 180 181 /* Use last 2 lwords in internal SRAM for bootcounter */ 182 #define CONFIG_BOOTCOUNT_LIMIT 183 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ 184 CONFIG_SRAM_SIZE) 185 186 #define CONFIG_HOSTNAME x600 187 #define CONFIG_UBI_PART ubi0 188 #define CONFIG_UBIFS_VOLUME rootfs 189 190 #define MTDIDS_DEFAULT "nand0=nand" 191 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 192 193 #define CONFIG_EXTRA_ENV_SETTINGS \ 194 "u-boot_addr=1000000\0" \ 195 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 196 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 197 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 198 " +${filesize};" \ 199 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 200 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ 201 " ${filesize};" \ 202 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 203 " +${filesize}\0" \ 204 "upd=run load update\0" \ 205 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ 206 "part=" __stringify(CONFIG_UBI_PART) "\0" \ 207 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ 208 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 209 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 210 " ${filesize}\0" \ 211 "upd_ubifs=run load_ubifs update_ubifs\0" \ 212 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 213 "ubi create ${vol} 4000000\0" \ 214 "netdev=eth0\0" \ 215 "rootpath=/opt/eldk-4.2/arm\0" \ 216 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 217 "nfsroot=${serverip}:${rootpath}\0" \ 218 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 219 "boot_part=0\0" \ 220 "altbootcmd=if test $boot_part -eq 0;then " \ 221 "echo Switching to partition 1!;" \ 222 "setenv boot_part 1;" \ 223 "else; " \ 224 "echo Switching to partition 0!;" \ 225 "setenv boot_part 0;" \ 226 "fi;" \ 227 "saveenv;boot\0" \ 228 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 229 "root=ubi0:rootfs rootfstype=ubifs\0" \ 230 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 231 "kernel_fs=/boot/uImage \0" \ 232 "kernel_addr=1000000\0" \ 233 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ 234 __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 235 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 236 "dtb_addr=1800000\0" \ 237 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 238 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 239 "addip=setenv bootargs ${bootargs} " \ 240 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 241 ":${hostname}:${netdev}:off panic=1\0" \ 242 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 243 "${baudrate}\0" \ 244 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 245 "net_nfs=run load_dtb load_kernel; " \ 246 "run nfsargs addip addcon addmtd addmisc;" \ 247 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 248 "mtdids=" MTDIDS_DEFAULT "\0" \ 249 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 250 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 251 " addcon addmisc addmtd;" \ 252 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 253 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 254 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 255 "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 256 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 257 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 258 "bootcmd=run nand_ubifs\0" \ 259 "\0" 260 261 /* Physical Memory Map */ 262 #define CONFIG_NR_DRAM_BANKS 1 263 #define PHYS_SDRAM_1 0x00000000 264 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 265 266 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 267 #define CONFIG_SRAM_BASE 0xd2800000 268 /* Preserve the last 2 lwords for the boot-counter */ 269 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) 270 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE 271 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE 272 273 #define CONFIG_SYS_INIT_SP_OFFSET \ 274 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 275 276 #define CONFIG_SYS_INIT_SP_ADDR \ 277 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 278 279 /* 280 * SPL related defines 281 */ 282 #define CONFIG_SPL_TEXT_BASE 0xd2800b00 283 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) 284 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 285 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" 286 287 #define CONFIG_SPL_FRAMEWORK 288 #define CONFIG_SPL_NOR_SUPPORT 289 #define CONFIG_SPL_SERIAL_SUPPORT 290 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ 291 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ 292 293 /* 294 * Please select/define only one of the following 295 * Each definition corresponds to a supported DDR chip. 296 * DDR configuration is based on the following selection 297 */ 298 #define CONFIG_DDR_MT47H64M16 1 299 #define CONFIG_DDR_MT47H32M16 0 300 #define CONFIG_DDR_MT47H128M8 0 301 302 /* 303 * Synchronous/Asynchronous operation of DDR 304 * 305 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 306 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 307 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 308 */ 309 #define CONFIG_DDR_2HCLK 1 310 #define CONFIG_DDR_HCLK 0 311 #define CONFIG_DDR_PLL2 0 312 313 /* 314 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 315 * or not. Modify/Add to only these macros to define new boot types 316 */ 317 #define USB_BOOT_SUPPORTED 0 318 #define PCIE_BOOT_SUPPORTED 0 319 #define SNOR_BOOT_SUPPORTED 1 320 #define NAND_BOOT_SUPPORTED 1 321 #define PNOR_BOOT_SUPPORTED 0 322 #define TFTP_BOOT_SUPPORTED 0 323 #define UART_BOOT_SUPPORTED 0 324 #define SPI_BOOT_SUPPORTED 0 325 #define I2C_BOOT_SUPPORTED 0 326 #define MMC_BOOT_SUPPORTED 0 327 328 #endif /* __CONFIG_H */ 329