1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4 * 5 * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* 30 * High Level Configuration Options 31 * (easy to change) 32 */ 33 #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 34 #define CONFIG_X600 /* on X600 board */ 35 36 #include <asm/arch/hardware.h> 37 38 /* Timer, HZ specific defines */ 39 #define CONFIG_SYS_HZ 1000 40 #define CONFIG_SYS_HZ_CLOCK 8300000 41 42 #define CONFIG_SYS_TEXT_BASE 0x00800040 43 #define CONFIG_SYS_FLASH_BASE 0xf8000000 44 /* Reserve 8KiB for SPL */ 45 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 46 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 47 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 48 CONFIG_SYS_SPL_LEN) 49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 50 #define CONFIG_SYS_MONITOR_LEN 0x60000 51 52 #define CONFIG_ENV_IS_IN_FLASH 53 54 /* Serial Configuration (PL011) */ 55 #define CONFIG_SYS_SERIAL0 0xD0000000 56 #define CONFIG_SYS_SERIAL1 0xD0080000 57 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 58 (void *)CONFIG_SYS_SERIAL1 } 59 #define CONFIG_PL011_SERIAL 60 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 61 #define CONFIG_CONS_INDEX 0 62 #define CONFIG_BAUDRATE 115200 63 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 64 57600, 115200 } 65 #define CONFIG_SYS_LOADS_BAUD_CHANGE 66 67 /* NOR FLASH config options */ 68 #define CONFIG_ST_SMI 69 #define CONFIG_SYS_MAX_FLASH_BANKS 1 70 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 71 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 72 #define CONFIG_SYS_MAX_FLASH_SECT 128 73 #define CONFIG_SYS_FLASH_EMPTY_INFO 74 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 75 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 76 77 /* NAND FLASH config options */ 78 #define CONFIG_NAND_FSMC 79 #define CONFIG_SYS_NAND_SELF_INIT 80 #define CONFIG_SYS_MAX_NAND_DEVICE 1 81 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 82 #define CONFIG_MTD_ECC_SOFT 83 #define CONFIG_SYS_FSMC_NAND_8BIT 84 #define CONFIG_SYS_NAND_ONFI_DETECTION 85 86 /* UBI/UBI config options */ 87 #define CONFIG_MTD_DEVICE 88 #define CONFIG_MTD_PARTITIONS 89 #define CONFIG_RBTREE 90 91 /* Ethernet config options */ 92 #define CONFIG_MII 93 #define CONFIG_DESIGNWARE_ETH 94 #define CONFIG_DW_SEARCH_PHY 95 #define CONFIG_NET_MULTI 96 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 97 #define CONFIG_DW_AUTONEG 98 #define CONFIG_PHY_ADDR 0 /* PHY address */ 99 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 100 101 #define CONFIG_SPEAR_GPIO 102 103 /* I2C config options */ 104 #define CONFIG_HARD_I2C 105 #define CONFIG_DW_I2C 106 #define CONFIG_SYS_I2C_SPEED 400000 107 #define CONFIG_SYS_I2C_SLAVE 0x02 108 #define CONFIG_I2C_CHIPADDRESS 0x50 109 110 #define CONFIG_RTC_M41T62 1 111 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 112 113 /* FPGA config options */ 114 #define CONFIG_FPGA 115 #define CONFIG_FPGA_XILINX 116 #define CONFIG_FPGA_SPARTAN3 117 #define CONFIG_FPGA_COUNT 1 118 119 /* 120 * Command support defines 121 */ 122 #define CONFIG_CMD_CACHE 123 #define CONFIG_CMD_DATE 124 #define CONFIG_CMD_DHCP 125 #define CONFIG_CMD_ENV 126 #define CONFIG_CMD_FPGA 127 #define CONFIG_CMD_GPIO 128 #define CONFIG_CMD_I2C 129 #define CONFIG_CMD_MEMORY 130 #define CONFIG_CMD_MII 131 #define CONFIG_CMD_MTDPARTS 132 #define CONFIG_CMD_NAND 133 #define CONFIG_CMD_NET 134 #define CONFIG_CMD_PING 135 #define CONFIG_CMD_RUN 136 #define CONFIG_CMD_SAVES 137 #define CONFIG_CMD_UBI 138 #define CONFIG_CMD_UBIFS 139 #define CONFIG_LZO 140 141 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 142 #include <config_cmd_default.h> 143 144 #define CONFIG_BOOTDELAY 3 145 146 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 147 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 148 149 /* 150 * U-Boot Environment placing definitions. 151 */ 152 #define CONFIG_ENV_SECT_SIZE 0x00010000 153 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 154 CONFIG_SYS_MONITOR_LEN) 155 #define CONFIG_ENV_SIZE 0x02000 156 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 157 CONFIG_ENV_SECT_SIZE) 158 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 159 160 /* Miscellaneous configurable options */ 161 #define CONFIG_ARCH_CPU_INIT 162 #define CONFIG_DISPLAY_CPUINFO 163 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 164 #define CONFIG_CMDLINE_TAG 165 #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 166 #define CONFIG_SETUP_MEMORY_TAGS 167 #define CONFIG_MISC_INIT_R 168 #define CONFIG_BOARD_LATE_INIT 169 #define CONFIG_LOOPW /* enable loopw command */ 170 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 171 #define CONFIG_ZERO_BOOTDELAY_CHECK 172 #define CONFIG_AUTOBOOT_KEYED 173 #define CONFIG_AUTOBOOT_STOP_STR " " 174 #define CONFIG_AUTOBOOT_PROMPT \ 175 "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay 176 177 #define CONFIG_SYS_MEMTEST_START 0x00800000 178 #define CONFIG_SYS_MEMTEST_END 0x04000000 179 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 180 #define CONFIG_IDENT_STRING "-SPEAr" 181 #define CONFIG_SYS_LONGHELP 182 #define CONFIG_SYS_PROMPT "X600> " 183 #define CONFIG_CMDLINE_EDITING 184 #define CONFIG_SYS_CBSIZE 256 185 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 186 sizeof(CONFIG_SYS_PROMPT) + 16) 187 #define CONFIG_SYS_MAXARGS 16 188 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 189 #define CONFIG_SYS_LOAD_ADDR 0x00800000 190 #define CONFIG_SYS_CONSOLE_INFO_QUIET 191 #define CONFIG_SYS_64BIT_VSPRINTF 192 193 /* Use last 2 lwords in internal SRAM for bootcounter */ 194 #define CONFIG_BOOTCOUNT_LIMIT 195 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 196 197 #define CONFIG_HOSTNAME x600 198 #define CONFIG_UBI_PART ubi0 199 #define CONFIG_UBIFS_VOLUME rootfs 200 201 #define xstr(s) str(s) 202 #define str(s) #s 203 204 #define MTDIDS_DEFAULT "nand0=nand" 205 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 206 207 #define CONFIG_EXTRA_ENV_SETTINGS \ 208 "u-boot_addr=1000000\0" \ 209 "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 210 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 211 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ 212 "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 213 "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ 214 " ${filesize};" \ 215 "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ 216 " +${filesize}\0" \ 217 "upd=run load update\0" \ 218 "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ 219 "part=" xstr(CONFIG_UBI_PART) "\0" \ 220 "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ 221 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 222 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 223 " ${filesize}\0" \ 224 "upd_ubifs=run load_ubifs update_ubifs\0" \ 225 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 226 "ubi create ${vol} 4000000\0" \ 227 "netdev=eth0\0" \ 228 "rootpath=/opt/eldk-4.2/arm\0" \ 229 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 230 "nfsroot=${serverip}:${rootpath}\0" \ 231 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 232 "boot_part=0\0" \ 233 "altbootcmd=if test $boot_part -eq 0;then " \ 234 "echo Switching to partition 1!;" \ 235 "setenv boot_part 1;" \ 236 "else; " \ 237 "echo Switching to partition 0!;" \ 238 "setenv boot_part 0;" \ 239 "fi;" \ 240 "saveenv;boot\0" \ 241 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 242 "root=ubi0:rootfs rootfstype=ubifs\0" \ 243 "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ 244 "kernel_fs=/boot/uImage \0" \ 245 "kernel_addr=1000000\0" \ 246 "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ 247 "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ 248 "dtb_addr=1800000\0" \ 249 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 250 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 251 "addip=setenv bootargs ${bootargs} " \ 252 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 253 ":${hostname}:${netdev}:off panic=1\0" \ 254 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 255 "${baudrate}\0" \ 256 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 257 "net_nfs=run load_dtb load_kernel; " \ 258 "run nfsargs addip addcon addmtd addmisc;" \ 259 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 260 "mtdids=" MTDIDS_DEFAULT "\0" \ 261 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 262 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 263 " addcon addmisc addmtd;" \ 264 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 265 "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \ 266 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 267 "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 268 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 269 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 270 "bootcmd=run nand_ubifs\0" \ 271 "\0" 272 273 /* Stack sizes */ 274 #define CONFIG_STACKSIZE (512 * 1024) 275 276 /* Physical Memory Map */ 277 #define CONFIG_NR_DRAM_BANKS 1 278 #define PHYS_SDRAM_1 0x00000000 279 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 280 281 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 282 #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 283 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 284 285 #define CONFIG_SYS_INIT_SP_OFFSET \ 286 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 287 288 #define CONFIG_SYS_INIT_SP_ADDR \ 289 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 290 291 /* 292 * SPL related defines 293 */ 294 #define CONFIG_SPL 295 #define CONFIG_SPL_TEXT_BASE 0xd2800b00 296 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 297 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" 298 299 #define CONFIG_SPL_SERIAL_SUPPORT 300 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ 301 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ 302 #define CONFIG_SPL_NO_PRINTF 303 304 /* 305 * Please select/define only one of the following 306 * Each definition corresponds to a supported DDR chip. 307 * DDR configuration is based on the following selection 308 */ 309 #define CONFIG_DDR_MT47H64M16 1 310 #define CONFIG_DDR_MT47H32M16 0 311 #define CONFIG_DDR_MT47H128M8 0 312 313 /* 314 * Synchronous/Asynchronous operation of DDR 315 * 316 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 317 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 318 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 319 */ 320 #define CONFIG_DDR_2HCLK 1 321 #define CONFIG_DDR_HCLK 0 322 #define CONFIG_DDR_PLL2 0 323 324 /* 325 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 326 * or not. Modify/Add to only these macros to define new boot types 327 */ 328 #define USB_BOOT_SUPPORTED 0 329 #define PCIE_BOOT_SUPPORTED 0 330 #define SNOR_BOOT_SUPPORTED 1 331 #define NAND_BOOT_SUPPORTED 1 332 #define PNOR_BOOT_SUPPORTED 0 333 #define TFTP_BOOT_SUPPORTED 0 334 #define UART_BOOT_SUPPORTED 0 335 #define SPI_BOOT_SUPPORTED 0 336 #define I2C_BOOT_SUPPORTED 0 337 #define MMC_BOOT_SUPPORTED 0 338 339 #endif /* __CONFIG_H */ 340