1 /* 2 * Copyright (C) 2009, STMicroelectronics - All Rights Reserved 3 * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics. 4 * 5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 18 #define CONFIG_X600 /* on X600 board */ 19 20 #include <asm/arch/hardware.h> 21 22 /* Timer, HZ specific defines */ 23 #define CONFIG_SYS_HZ_CLOCK 8300000 24 25 #define CONFIG_SYS_TEXT_BASE 0x00800040 26 #define CONFIG_SYS_FLASH_BASE 0xf8000000 27 /* Reserve 8KiB for SPL */ 28 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 29 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 30 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 31 CONFIG_SYS_SPL_LEN) 32 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 34 #define CONFIG_SYS_MONITOR_LEN 0x60000 35 36 /* Serial Configuration (PL011) */ 37 #define CONFIG_SYS_SERIAL0 0xD0000000 38 #define CONFIG_SYS_SERIAL1 0xD0080000 39 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 40 (void *)CONFIG_SYS_SERIAL1 } 41 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 42 #define CONFIG_CONS_INDEX 0 43 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 44 57600, 115200 } 45 #define CONFIG_SYS_LOADS_BAUD_CHANGE 46 47 /* NOR FLASH config options */ 48 #define CONFIG_ST_SMI 49 #define CONFIG_SYS_MAX_FLASH_BANKS 1 50 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 51 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 52 #define CONFIG_SYS_MAX_FLASH_SECT 128 53 #define CONFIG_SYS_FLASH_EMPTY_INFO 54 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 55 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 56 57 /* NAND FLASH config options */ 58 #define CONFIG_NAND_FSMC 59 #define CONFIG_SYS_NAND_SELF_INIT 60 #define CONFIG_SYS_MAX_NAND_DEVICE 1 61 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 62 #define CONFIG_MTD_ECC_SOFT 63 #define CONFIG_SYS_FSMC_NAND_8BIT 64 #define CONFIG_SYS_NAND_ONFI_DETECTION 65 #define CONFIG_NAND_ECC_BCH 66 67 /* UBI/UBI config options */ 68 #define CONFIG_MTD_DEVICE 69 #define CONFIG_MTD_PARTITIONS 70 71 /* Ethernet config options */ 72 #define CONFIG_MII 73 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 74 #define CONFIG_PHY_ADDR 0 /* PHY address */ 75 76 #define CONFIG_SPEAR_GPIO 77 78 /* I2C config options */ 79 #define CONFIG_SYS_I2C 80 #define CONFIG_SYS_I2C_BASE 0xD0200000 81 #define CONFIG_SYS_I2C_SPEED 400000 82 #define CONFIG_SYS_I2C_SLAVE 0x02 83 #define CONFIG_I2C_CHIPADDRESS 0x50 84 85 #define CONFIG_RTC_M41T62 1 86 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 87 88 /* FPGA config options */ 89 #define CONFIG_FPGA 90 #define CONFIG_FPGA_XILINX 91 #define CONFIG_FPGA_SPARTAN3 92 #define CONFIG_FPGA_COUNT 1 93 94 /* USB EHCI options */ 95 #define CONFIG_USB_EHCI_SPEAR 96 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 97 98 /* 99 * U-Boot Environment placing definitions. 100 */ 101 #define CONFIG_ENV_SECT_SIZE 0x00010000 102 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 103 CONFIG_SYS_MONITOR_LEN) 104 #define CONFIG_ENV_SIZE 0x02000 105 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 106 CONFIG_ENV_SECT_SIZE) 107 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 108 109 /* Miscellaneous configurable options */ 110 #define CONFIG_ARCH_CPU_INIT 111 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 112 #define CONFIG_CMDLINE_TAG 113 #define CONFIG_SETUP_MEMORY_TAGS 114 #define CONFIG_MISC_INIT_R 115 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 116 117 #define CONFIG_SYS_MEMTEST_START 0x00800000 118 #define CONFIG_SYS_MEMTEST_END 0x04000000 119 #define CONFIG_SYS_MALLOC_LEN (8 << 20) 120 #define CONFIG_SYS_LONGHELP 121 #define CONFIG_CMDLINE_EDITING 122 #define CONFIG_AUTO_COMPLETE 123 #define CONFIG_SYS_LOAD_ADDR 0x00800000 124 125 /* Use last 2 lwords in internal SRAM for bootcounter */ 126 #define CONFIG_BOOTCOUNT_LIMIT 127 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ 128 CONFIG_SRAM_SIZE) 129 130 #define CONFIG_HOSTNAME x600 131 #define CONFIG_UBI_PART ubi0 132 #define CONFIG_UBIFS_VOLUME rootfs 133 134 #define CONFIG_EXTRA_ENV_SETTINGS \ 135 "u-boot_addr=1000000\0" \ 136 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 137 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 138 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 139 " +${filesize};" \ 140 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 141 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ 142 " ${filesize};" \ 143 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 144 " +${filesize}\0" \ 145 "upd=run load update\0" \ 146 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ 147 "part=" __stringify(CONFIG_UBI_PART) "\0" \ 148 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ 149 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 150 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 151 " ${filesize}\0" \ 152 "upd_ubifs=run load_ubifs update_ubifs\0" \ 153 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 154 "ubi create ${vol} 4000000\0" \ 155 "netdev=eth0\0" \ 156 "rootpath=/opt/eldk-4.2/arm\0" \ 157 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 158 "nfsroot=${serverip}:${rootpath}\0" \ 159 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 160 "boot_part=0\0" \ 161 "altbootcmd=if test $boot_part -eq 0;then " \ 162 "echo Switching to partition 1!;" \ 163 "setenv boot_part 1;" \ 164 "else; " \ 165 "echo Switching to partition 0!;" \ 166 "setenv boot_part 0;" \ 167 "fi;" \ 168 "saveenv;boot\0" \ 169 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 170 "root=ubi0:rootfs rootfstype=ubifs\0" \ 171 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 172 "kernel_fs=/boot/uImage \0" \ 173 "kernel_addr=1000000\0" \ 174 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ 175 __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 176 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 177 "dtb_addr=1800000\0" \ 178 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 179 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 180 "addip=setenv bootargs ${bootargs} " \ 181 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 182 ":${hostname}:${netdev}:off panic=1\0" \ 183 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 184 "${baudrate}\0" \ 185 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 186 "net_nfs=run load_dtb load_kernel; " \ 187 "run nfsargs addip addcon addmtd addmisc;" \ 188 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 189 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ 190 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 191 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 192 " addcon addmisc addmtd;" \ 193 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 194 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 195 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 196 "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 197 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 198 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 199 "bootcmd=run nand_ubifs\0" \ 200 "\0" 201 202 /* Physical Memory Map */ 203 #define CONFIG_NR_DRAM_BANKS 1 204 #define PHYS_SDRAM_1 0x00000000 205 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 206 207 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 208 #define CONFIG_SRAM_BASE 0xd2800000 209 /* Preserve the last 2 lwords for the boot-counter */ 210 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) 211 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE 212 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE 213 214 #define CONFIG_SYS_INIT_SP_OFFSET \ 215 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 216 217 #define CONFIG_SYS_INIT_SP_ADDR \ 218 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 219 220 /* 221 * SPL related defines 222 */ 223 #define CONFIG_SPL_TEXT_BASE 0xd2800b00 224 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) 225 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 226 227 #define CONFIG_SPL_FRAMEWORK 228 229 /* 230 * Please select/define only one of the following 231 * Each definition corresponds to a supported DDR chip. 232 * DDR configuration is based on the following selection 233 */ 234 #define CONFIG_DDR_MT47H64M16 1 235 #define CONFIG_DDR_MT47H32M16 0 236 #define CONFIG_DDR_MT47H128M8 0 237 238 /* 239 * Synchronous/Asynchronous operation of DDR 240 * 241 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 242 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 243 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 244 */ 245 #define CONFIG_DDR_2HCLK 1 246 #define CONFIG_DDR_HCLK 0 247 #define CONFIG_DDR_PLL2 0 248 249 /* 250 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 251 * or not. Modify/Add to only these macros to define new boot types 252 */ 253 #define USB_BOOT_SUPPORTED 0 254 #define PCIE_BOOT_SUPPORTED 0 255 #define SNOR_BOOT_SUPPORTED 1 256 #define NAND_BOOT_SUPPORTED 1 257 #define PNOR_BOOT_SUPPORTED 0 258 #define TFTP_BOOT_SUPPORTED 0 259 #define UART_BOOT_SUPPORTED 0 260 #define SPI_BOOT_SUPPORTED 0 261 #define I2C_BOOT_SUPPORTED 0 262 #define MMC_BOOT_SUPPORTED 0 263 264 #endif /* __CONFIG_H */ 265